Sub-band structure engineering for advanced CMOS channels

Solid-State Electronics

Volumn 49, Issue 5, 2005, Pages 684-694

  Takagi, Shin Ichi ^a,b   Mizuno, T ^a,c   Tezuka, T ^a   Sugiyama, N ^a   Nakaharai, S ^a   Numata, T ^a   Koga, J ^a   Uchida, K ^a  

^a TOSHIBA CORPORATION   (Japan)

^b UNIVERSITY OF TOKYO   (Japan)

^c KANAGAWA UNIVERSITY   (Japan)

Author keywords

Ballistic transport; Mobility; SOI; Strained Si; Sub band

Indexed keywords

CONSTRAINT THEORY; ELECTRIC CONDUCTIVITY; ELECTRON MOBILITY; ELECTRON TRANSPORT PROPERTIES; INTERFACES (MATERIALS); MOSFET DEVICES; SILICON; SILICON ON INSULATOR TECHNOLOGY; STRAIN;

BALLISTIC TRANSPORT; CMOS CHANNELS; GE-ON-INSULATOR (GOI) TECHNOLOGY; STRAINED SI; SUB-BAND;

CMOS INTEGRATED CIRCUITS;

EID: 14844323138     PISSN: 00381101     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sse.2004.08.020     Document Type: Conference Paper

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