Enhanced performance of strained-Si MOSFETs on CMP SiGe virtual substrate

Technical Digest - International Electron Devices Meeting

Volumn , Issue , 2001, Pages 737-740

  Sugii, Nobuyuki ^a   Hisamoto, Digh ^a   Washio, Katsuyoshi ^a   Yokoyama, Natsuki ^a   Kimura, Shin'ichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ATOMIC FORCE MICROSCOPY; CHEMICAL MECHANICAL POLISHING; CMOS INTEGRATED CIRCUITS; ELECTRON MOBILITY; HOLE MOBILITY; INTEGRATED CIRCUIT MANUFACTURE; RELAXATION PROCESSES; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR GROWTH; SUBSTRATES; SURFACE ROUGHNESS;

BUFFER LAYER; CHEMICAL MECHANICAL PLANARIZATION; CROSS HATCHING; ROUGHNESS SCATTERING; STRAIN RELAXATION; VIRTUAL SUBSTRATES;

MOSFET DEVICES;

EID: 0035714397     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)

1. Transconductance enhancement in deep submicron strained-Si n-MOSFETs
2. Electron and hole mobility enhancement in strained-Si MOSFETs on SiGe-on-insulator substrates fabricated by SIMOX technology
3. Carrier mobility enhancement in strained Si-on-insulator fabricated by wafer bonding
4. Strained Si NMOSFETs for high performance CMOS technology
5. High-mobility strained-Si PMOSFETs
6. x buffer layer on mobility enhancement in a strained-Si n-channel metal-oxide-semiconductor field-effect transistor
7. Elimination of parasitic channels in strained-Si p-channel metal-oxide-semiconductor field-effect transistors
8. 1-xGe/Si heterostructures
9. Scattering from strain variations in high-mobility Si/SiGe heterostructures
10. 0.3 heterostructure
11. An ac conductance technique for measuring self-heating in SOI MOSFETs