-
1
-
-
0028483827
-
A 25-MS/s 8-bit CMOS A/D converter for embedded application
-
M. Pelgrom, J. van Rens, M. Vertregt, and M. Dijkstra, "A 25-MS/s 8-bit CMOS A/D converter for embedded application," IEEE J. Solid-State Circuits, vol. 29, pp. 879-886, 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 879-886
-
-
Pelgrom, M.1
Van Rens, J.2
Vertregt, M.3
Dijkstra, M.4
-
3
-
-
0343930350
-
A two-residue architecture for multistage ADC's
-
C. Mangelsdorf, H. Malik, S. Lee, S. Hisano, and M. Martin, "A two-residue architecture for multistage ADC's," ISSCC Digest of Technical Papers, pp. 64-65, 1993.
-
(1993)
ISSCC Digest of Technical Papers
, pp. 64-65
-
-
Mangelsdorf, C.1
Malik, H.2
Lee, S.3
Hisano, S.4
Martin, M.5
-
4
-
-
0024754187
-
Matching properties of MOS transistors
-
M. Pelgrom, A. Duinmaijer, and A. Welbers, "Matching properties of MOS transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1433-1440
-
-
Pelgrom, M.1
Duinmaijer, A.2
Welbers, A.3
-
5
-
-
0032272385
-
Transistor matching in analog applications,"
-
M. Pelgrom, H. Tuinhout, and M. Vertregt, "Transistor matching in analog applications," IEDM Technical Digest, pp. 34.1.1-34.1.4, 1998.
-
(1998)
IEDM Technical Digest
, pp. 3411-3414
-
-
Pelgrom, M.1
Tuinhout, H.2
Vertregt, M.3
-
6
-
-
0033314182
-
Accurate thermal noise model for deep-submicron CMOS
-
A. Scholten, H. Tromp, L. Tiemeijer, R. van Langevelde, R. Havens, P. de Vreede, R. Roes, P. Woerlee, A. Montree, and D. Klaassen, "Accurate thermal noise model for deep-submicron CMOS," IEDM Technical Digest, pp. 155-158, 1999.
-
(1999)
IEDM Technical Digest
, pp. 155-158
-
-
Scholten, A.1
Tromp, H.2
Tiemeijer, L.3
Van Langevelde, R.4
Havens, R.5
De Vreede, P.6
Roes, R.7
Woerlee, P.8
Montree, A.9
Klaassen, D.10
-
8
-
-
33746329247
-
Scalable high speed analog circuit design
-
J. Huijsing, M. Steyaert, and A. van Roermund, eds. Kluwer Academic Publishers
-
M. Vertregt and P. Scholtens, "Scalable high speed analog circuit design," in Analog circuit design (J. Huijsing, M. Steyaert, and A. van Roermund, eds.), pp. 3-21, Kluwer Academic Publishers, 2004.
-
(2004)
Analog Circuit Design
, pp. 3-21
-
-
Vertregt, M.1
Scholtens, P.2
-
10
-
-
84891978659
-
High-speed A/D converter monolithic techniques
-
D. R. Breuer, "High-speed A/D converter monolithic techniques," ISSCC Digest of Technical Papers, pp. 146-147, 1972.
-
(1972)
ISSCC Digest of Technical Papers
, pp. 146-147
-
-
Breuer, D.R.1
-
12
-
-
0018678393
-
A monolithic video A/D converter
-
J. G. Peterson, "A monolithic video A/D converter," IEEE J. Solid-State Circuits, vol. 6, pp. 932-937, 1979.
-
(1979)
IEEE J. Solid-State Circuits
, vol.6
, pp. 932-937
-
-
Peterson, J.G.1
-
13
-
-
0035058178
-
A 6b 1.1GSample/s CMOS A/D converter
-
G. Geelen, "A 6b 1.1GSample/s CMOS A/D converter," ISSCC Digest of Technical Papers, pp. 128-129, 2001.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 128-129
-
-
Geelen, G.1
-
14
-
-
0036917305
-
A 6-bit 1.6-GS/s flash ADC in 0.18-μ m CMOS using averaging termination
-
P. Scholtens and M. Vertregt, "A 6-bit 1.6-GS/s flash ADC in 0.18-μ m CMOS using averaging termination," IEEE J. Solid-State Circuits, vol. 37, pp. 1599-1609, 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1599-1609
-
-
Scholtens, P.1
Vertregt, M.2
-
15
-
-
0024936455
-
A 10-bit 60 MSps flash ADC
-
C. Lane, "A 10-bit 60 MSps flash ADC," Proc. BTCM, pp. 44-47, 1989.
-
(1989)
Proc. BTCM
, pp. 44-47
-
-
Lane, C.1
-
16
-
-
0030411456
-
An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing
-
A. Venes and R. van de Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1846-1853
-
-
Venes, A.1
Plassche De R.Van2
-
17
-
-
0003135251
-
A technique for reducing differential nonlin-earity errors in flash A/D converters
-
K. Kattmann and J. Barrow, "A technique for reducing differential nonlin-earity errors in flash A/D converters," ISSCC Digest of Technical Papers, pp. 170-171, 1991.
-
(1991)
ISSCC Digest of Technical Papers
, pp. 170-171
-
-
Kattmann, K.1
Barrow, J.2
-
18
-
-
0027887674
-
A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC
-
K. Kusumoto, A. Matsuzawa, and K. Murata, "A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1200-1206, 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 1200-1206
-
-
Kusumoto, K.1
Matsuzawa, A.2
Murata, K.3
-
20
-
-
0023570553
-
An 8-bit video ADC incorporating folding and interpolation techniques
-
R. van de Grift, I. Rutten, and M. van der Veen, "An 8-bit video ADC incorporating folding and interpolation techniques," IEEE J. Solid-State Circuits, vol. 22, pp. 944-953, 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, pp. 944-953
-
-
Grift De R.Van1
Rutten, I.2
Veen Der M.Van3
-
22
-
-
0029510025
-
A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
-
B. Nauta and A. Venes, "A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 1302-1308, 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 1302-1308
-
-
Nauta, B.1
Venes, A.2
-
23
-
-
0031378861
-
A 12-b, 60-MSample/s cascaded folding and interpolating ADC
-
P. Vorenkamp and R. Roovers, "A 12-b, 60-MSample/s cascaded folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 1876-1886
-
-
Vorenkamp, P.1
Roovers, R.2
-
26
-
-
0022306670
-
An 8-MHz CMOS subranging 8-bit A/D converter
-
A. Dingwall and V. Zazzu, "An 8-MHz CMOS subranging 8-bit A/D converter," IEEE J. Solid-State Circuits, vol. 20, pp. 1138-1143, 1985.
-
(1985)
IEEE J. Solid-State Circuits
, vol.20
, pp. 1138-1143
-
-
Dingwall, A.1
Zazzu, V.2
-
27
-
-
0034476030
-
A 14-bit 100-MSample/s subranging ADC
-
C. Moreland, F. Murden, M. Elliott, J. Young, M. Hensley, and R. Stop, "A 14-bit 100-MSample/s subranging ADC," IEEE J. Solid-State Circuits, vol. 35, pp. 1791-1798, 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1791-1798
-
-
Moreland, C.1
Murden, F.2
Elliott, M.3
Young, J.4
Hensley, M.5
Stop, R.6
-
28
-
-
0033280251
-
A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μ m CMOS
-
H. van der Ploeg and R. Remmers, "A 3.3-V, 10-b, 25-MSample/s two-step ADC in 0.35-μ m CMOS," IEEE J. Solid-State Circuits, vol. 34, pp. 1803-1811, 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 1803-1811
-
-
Ploeg Der H.Van1
Remmers, R.2
-
29
-
-
0023599417
-
A pipelined 5-MSample/s 9-bit analog-to-digital converter
-
S. Lewis and P. Gray, "A pipelined 5-MSample/s 9-bit analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 22, pp. 954-961, 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, pp. 954-961
-
-
Lewis, S.1
Gray, P.2
-
30
-
-
0033872609
-
A 55-mW, 10-bit, 40-MSample/s Nyquist-rate CMOS ADC
-
I. Mehr and L. Singer, "A 55-mW, 10-bit, 40-MSample/s Nyquist-rate CMOS ADC," IEEE J. Solid-State Circuits, vol. 35, pp. 318-325, 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 318-325
-
-
Mehr, I.1
Singer, L.2
-
31
-
-
0030106088
-
A power optimized 13-b 5 MSample/s pipelined Analog-to-digital converter in 1.2 μ m CMOS
-
D. Cline and P. Gray, "A power optimized 13-b 5 MSample/s pipelined Analog-to-digital converter in 1.2 μ m CMOS," IEEE J. Solid-State Circuits, vol. 31, pp. 294-303, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 294-303
-
-
Cline, D.1
Gray, P.2
-
32
-
-
0020301923
-
Random errors in MOS capacitors
-
J.-B. Shyu, G. Temes, and K. Yao, "Random errors in MOS capacitors," IEEE J. Solid-State Circuits, vol. 6, pp. 1070-1076, 1982.
-
(1982)
IEEE J. Solid-State Circuits
, vol.6
, pp. 1070-1076
-
-
Shyu, J.-B.1
Temes, G.2
Yao, K.3
-
33
-
-
0035693618
-
A 3-V 340-mW 14b 75-Msample/s CMOS ADC with85-dB SFDR at Nyquist input
-
W. Yang, D. Kelly, I. Mehr, M. Sayuk, and L. Singer, "A 3-V 340-mW 14b 75-Msample/s CMOS ADC with85-dB SFDR at Nyquist input," IEEE J. Solid-State Circuits, vol. 36, pp. 1931-1936, 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1931-1936
-
-
Yang, W.1
Kelly, D.2
Mehr, I.3
Sayuk, M.4
Singer, L.5
-
34
-
-
0032664038
-
A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline anlog-to-digital converter
-
A. Abo and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline anlog-to-digital converter," IEEE J. Solid-State Circuits, vol. 34, pp. 599-606, 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 599-606
-
-
Abo, A.1
Gray, P.2
-
35
-
-
0034428237
-
A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120MHz,"
-
L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12 b 65 MSample/s CMOS ADC with 82 dB SFDR at 120MHz," ISSCC Digest of Technical Papers, pp. 38-39, 2000.
-
(2000)
ISSCC Digest of Technical Papers
, pp. 38-39
-
-
Singer, L.1
Ho, S.2
Timko, M.3
Kelly, D.4
-
36
-
-
0035060903
-
A 3V 340mW 14b 75MSps CMOS ADC with 85dB SFDR at Nyquist
-
D. Kelly, I. Mehr, M. Sayuk, and L. Singer, "A 3V 340mW 14b 75MSps CMOS ADC with 85dB SFDR at Nyquist," ISSCC Digest of Technical Papers, pp. 134-135, 2001.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 134-135
-
-
Kelly, D.1
Mehr, I.2
Sayuk, M.3
Singer, L.4
-
37
-
-
0348233280
-
A 12-bit 75MS/s pipelined ADC using open-loop residue amplification
-
B. Murmann and B. Boser, "A 12-bit 75MS/s pipelined ADC using open-loop residue amplification," IEEE J. Solid-State Circuits, vol. 38, pp. 2040-2050, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 2040-2050
-
-
Murmann, B.1
Boser, B.2
-
38
-
-
0016620207
-
All-MOS charge redistribution analog-to-digital conversion techniques-part i
-
J. McCreary and P. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques-part I," IEEE J. Solid-State Circuits, vol. 10, pp. 371-379, 1975.
-
(1975)
IEEE J. Solid-State Circuits
, vol.10
, pp. 371-379
-
-
McCreary, J.1
Gray, P.2
-
39
-
-
0022900276
-
A 12-bit succesive-approximation-type ADC with digital error correction
-
K. Bacrania, "A 12-bit succesive-approximation-type ADC with digital error correction," IEEE J. Solid-State Circuits, vol. 21, pp. 1016-1025, 1986.
-
(1986)
IEEE J. Solid-State Circuits
, vol.21
, pp. 1016-1025
-
-
Bacrania, K.1
-
40
-
-
0036116461
-
A 1.2 v 10 b 20 MSample/s non-binary succesive approximation ADC in 0.13μ m CMOS
-
F. Kuttner, "A 1.2 V 10 b 20 MSample/s non-binary succesive approximation ADC in 0.13μ m CMOS," ISSCC Digest of Technical Papers, pp. 176-177, 2002.
-
(2002)
ISSCC Digest of Technical Papers
, pp. 176-177
-
-
Kuttner, F.1
-
41
-
-
0036912822
-
An embedded 0.8 V/480 μ W 6b/22 MHz flash ADC in 0.13-μ m digital CMOS process using a nonlinear double interpolation technique
-
J. Lin and B. Haroun, "An embedded 0.8 V/480 μ W 6b/22 MHz flash ADC in 0.13-μ m digital CMOS process using a nonlinear double interpolation technique," IEEE J. Solid-State Circuits, vol. 37, pp. 1610-1617, 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 1610-1617
-
-
Lin, J.1
Haroun, B.2
-
43
-
-
0036503232
-
A digital" 6-bit ADC in 0.25-μ m CMOS
-
C. Donovan and M. Flynn, "A digital" 6-bit ADC in 0.25-μ m CMOS," IEEE J. Solid-State Circuits, vol. 37, pp. 432-437, 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 432-437
-
-
Donovan, C.1
Flynn, M.2
-
44
-
-
0033364066
-
A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications
-
I. Mehr and D. Dalton, "A 500-MSample/s, 6-bit Nyquist-rate ADC for disk-drive read-channel applications," IEEE J. Solid-State Circuits, vol. 34, pp. 912-920, 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 912-920
-
-
Mehr, I.1
Dalton, D.2
-
45
-
-
0034476097
-
A dual-mode 700-MSample/s 6-bit 200-MSample/s 7-bit A/D converter in a 0.25-μ m digital CMOS process
-
K. Nagaraj, D. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T. Viswanathan, "A dual-mode 700-MSample/s 6-bit 200-MSample/s 7-bit A/D converter in a 0.25-μ m digital CMOS process," IEEE J. Solid-State Circuits, vol. 35, pp. 1760-1768, 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1760-1768
-
-
Nagaraj, K.1
Martin, D.2
Wolfe, M.3
Chattopadhyay, R.4
Pavan, S.5
Cancio, J.6
Viswanathan, T.7
-
46
-
-
0035696160
-
A 6 b 1.3 GSample/s A/D converter in 0.35 μ m CMOS
-
M. Choi and A. Abidi, "A 6 b 1.3 GSample/s A/D converter in 0.35 μ m CMOS," IEEE J. Solid-State Circuits, vol. 36, pp. 1847-1858, 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1847-1858
-
-
Choi, M.1
Abidi, A.2
-
47
-
-
0033169556
-
Efficient 6-bit A/D converter using a 1-bit folding front end
-
K. Nagaraj, F. Chen, T. Le, and T. R. Viswanathan, "Efficient 6-bit A/D converter using a 1-bit folding front end," IEEE J. Solid-State Circuits, vol. 34, pp. 1056-1062, 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 1056-1062
-
-
Nagaraj, K.1
Chen, F.2
Le, T.3
Viswanathan, T.R.4
-
48
-
-
0037344281
-
Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter
-
K. Uyttenhove, J. Vandenbussche, E. Lauwers, G. Gielen, and M. Steyaert, "Design techniques and implementation of an 8-bit 200-MS/s interpolating/averaging CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 38, pp. 483-494, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 483-494
-
-
Uyttenhove, K.1
Vandenbussche, J.2
Lauwers, E.3
Gielen, G.4
Steyaert, M.5
-
49
-
-
2442637540
-
A 1.8 v 1.6 GS/s 8b Self-Calibrating Folding ADC with 7.26 ENOB at Nyquist Frequency
-
R. Taft, C. Menkus, M. Tursi, O. Hidri, and V. Pons, "A 1.8 V 1.6 GS/s 8b Self-Calibrating Folding ADC with 7.26 ENOB at Nyquist Frequency," ISSCC Digest of Technical Papers, vol. 47, pp. 252-253, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 252-253
-
-
Taft, R.1
Menkus, C.2
Tursi, M.3
Hidri, O.4
Pons, V.5
-
50
-
-
2442648846
-
An 8 b 600 MS/s 200 mW CMOS folding A/D converter using an amplifier preset technique
-
G. Geelen and E. Paulus, "An 8 b 600 MS/s 200 mW CMOS Folding A/D Converter Using an Amplifier Preset Technique," ISSCC Digest of Technical Papers, vol. 47, pp. 254-255, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 254-255
-
-
Geelen, G.1
Paulus, E.2
-
51
-
-
0033725314
-
An 8-bit 125 MS/s CMOS folding ADC for gigabit ethernet LSI
-
K. Yoon, J. Lee, D.-K. Jeong, and W. Kim, "An 8-bit 125 MS/s CMOS folding ADC for gigabit ethernet LSI," VLSI Digest of Technical Papers, pp. 212-213, 2000.
-
(2000)
VLSI Digest of Technical Papers
, pp. 212-213
-
-
Yoon, K.1
Lee, J.2
Jeong, D.-K.3
Kim, W.4
-
52
-
-
0035117766
-
An 8-bit 10 MS/s folding and interpolating ADC using the continous-time auto-zero technique
-
M.-H. Liu and S.-I. Liu, "An 8-bit 10 MS/s folding and interpolating ADC using the continous-time auto-zero technique," IEEE J. Solid-State Circuits, vol. 36, pp. 122-128, 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 122-128
-
-
Liu, M.-H.1
Liu, S.-I.2
-
53
-
-
0042697051
-
A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC
-
Y. Li and E. Sánchez-Sinencio, "A wide input bandwidth 7-bit 300-MSample/s folding and current-mode interpolating ADC," IEEE J. Solid-State Circuits, vol. 38, pp. 1405-1410, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 1405-1410
-
-
Li, Y.1
Sánchez-Sinencio, E.2
-
54
-
-
0035273821
-
A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 v down to 2.2 v
-
R. Taft and M. Tursi, "A 100-MS/s 8-b CMOS subranging ADC with sustained parametric performance from 3.8 V down to 2.2 V," IEEE J. Solid-State Circuits, vol. 36, pp. 331-338, 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 331-338
-
-
Taft, R.1
Tursi, M.2
-
55
-
-
0033281188
-
A 75-mW. 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist
-
B. Brandt and J. Lutsky, "A 75-mW. 10-b, 20-MSPS CMOS subranging ADC with 9.5 effective bits at Nyquist," IEEE J. Solid-State Circuits, vol. 34, pp. 1788-1795, 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 1788-1795
-
-
Brandt, B.1
Lutsky, J.2
-
56
-
-
0034480240
-
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μ m CMOS with over 80-dB SFDR
-
H. Pan, M. Segami, M. Choi, J. Cao, and A. Abidi, "A 3.3-V 12-b 50-MS/s A/D converter in 0.6-μ m CMOS with over 80-dB SFDR," IEEE J. Solid-State Circuits, vol. 35, pp. 1769-1780, 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1769-1780
-
-
Pan, H.1
Segami, M.2
Choi, M.3
Cao, J.4
Abidi, A.5
-
57
-
-
0034482479
-
A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming
-
M.-J. Choe, B.-S. Song, and K. Bacrania, "A 13-b 40-MSamples/s CMOS pipelined folding ADC with background offset trimming," IEEE J. Solid-State Circuits, vol. 35, pp. 1781-1790, 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 1781-1790
-
-
Choe, M.-J.1
Song, B.-S.2
Bacrania, K.3
-
58
-
-
0035693616
-
2 with mixed-signal chopping and calibration
-
2 with mixed-signal chopping and calibration," IEEE J. Solid-State Circuits, vol. 36, pp. 1859-1867, 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 1859-1867
-
-
Ploeg Der H.Van1
Hoogzaad, G.2
Termeer, H.3
Vertregt, M.4
Roovers, R.5
-
59
-
-
2542460411
-
A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13 m Digital CMOS
-
B. Hernes, A. Briskemyr, T. Andersen, F. Telstø, T. Bonnerud, and O. Moldsvor, "A 1.2V 220MS/s 10b Pipeline ADC Implemented in 0.13 m Digital CMOS," ISSCC Digest of Technical Papers, vol. 47, pp. 256-257, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 256-257
-
-
Hernes, B.1
Briskemyr, A.2
Andersen, T.3
Telstø, F.4
Bonnerud, T.5
Moldsvor, O.6
-
60
-
-
0036108540
-
A 4 GSample/s 8b ADC in 0.35 μm CMOS
-
K. Poulton, R. Neff, A. Muto, W. Liu, A. Burstein, and M. Heshami, "A 4 GSample/s 8b ADC in 0.35 μ m CMOS," ISSCC Digest of Technical Papers, pp. 166-167, 2002.
-
(2002)
ISSCC Digest of Technical Papers
, pp. 166-167
-
-
Poulton, K.1
Neff, R.2
Muto, A.3
Liu, W.4
Burstein, A.5
Heshami, M.6
-
61
-
-
0037630792
-
A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μ m CMOS
-
K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jew-ett, J. Pernillo, C. Tan, and A. Montijo, "A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 μ m CMOS," ISSCC Digest of Technical Papers, pp. 318-319, 2003.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 318-319
-
-
Poulton, K.1
Neff, R.2
Setterberg, B.3
Wuppermann, B.4
Kopley, T.5
Jew-Ett, R.6
Pernillo, J.7
Tan, C.8
Montijo, A.9
-
62
-
-
0038306334
-
A 10 b 150 MS/s 123 mW 0.18 μ m CMOS pipelined ADC,"
-
S.-M. Yoo, J.-B. Park, H.-S. Yang, H.-H. Bae, K.-H. Moon, H.-J. Park, S.-H. Lee, and J.-H. Kim, "A 10 b 150 MS/s 123 mW 0.18 μ m CMOS pipelined ADC," ISSCC Digest of Technical Papers, pp. 326-327, 2003.
-
(2003)
ISSCC Digest of Technical Papers
, pp. 326-327
-
-
Yoo, S.-M.1
Park, J.-B.2
Yang, H.-S.3
Bae, H.-H.4
Moon, K.-H.5
Park, H.-J.6
Lee, S.-H.7
Kim, J.-H.8
-
63
-
-
0038155505
-
A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system
-
K. Kaviani, O. Oralkan, P. Khuri-Yakub, and B. Wooley, "A multichannel pipeline analog-to-digital converter for an integrated 3-D ultrasound imaging system," IEEE J. Solid-State Circuits, vol. 38, pp. 1266-1270, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 1266-1270
-
-
Kaviani, K.1
Oralkan, O.2
Khuri-Yakub, P.3
Wooley, B.4
-
64
-
-
0037319649
-
A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture
-
D. Miyazaki, S. Kawahito, and M. Furuta, "A 10-b 30-MS/s low-power pipelined CMOS A/D converter using a pseudodifferential architecture," IEEE J. Solid-State Circuits, vol. 38, pp. 369-373, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 369-373
-
-
Miyazaki, D.1
Kawahito, S.2
Furuta, M.3
-
65
-
-
0035058521
-
A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 v power supply
-
Y.-I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, "A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply," ISSCC Digest of Technical Papers, pp. 130-131, 2001.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 130-131
-
-
Park, Y.-I.1
Karthikeyan, S.2
Tsay, F.3
Bartolome, E.4
-
66
-
-
0036106114
-
A 16 mW 30 MSample/s 10 b pipelined A/D converter using a pseudo-differential architecture
-
D. Miyazaki, M. Furuta, and S. Kawahito, "A 16 mW 30 MSample/s 10 b pipelined A/D converter using a pseudo-differential architecture," ISSCC Digest of Technical Papers, pp. 174-175, 2002.
-
(2002)
ISSCC Digest of Technical Papers
, pp. 174-175
-
-
Miyazaki, D.1
Furuta, M.2
Kawahito, S.3
-
67
-
-
0346972345
-
A 69-mW 10bit 80-MSample/s pipelined CMOS ADC
-
B.-M. Min, P. Kim, F. Bowman, D. Boisvert, and A. Aude, "A 69-mW 10bit 80-MSample/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 38, pp. 2031-2039, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 2031-2039
-
-
Min, B.-M.1
Kim, P.2
Bowman, F.3
Boisvert, D.4
Aude, A.5
-
68
-
-
0033280879
-
An 8 b 500 MS/s full Nyquist cascade A/D converter
-
K. Irie, N. Kusayanagi, T. Kawachi, T. Nishibu, and Y. Matsumori, "An 8 b 500 MS/s full Nyquist cascade A/D converter," VLSI Digest of Technical Papers, pp. 77-78, 1999.
-
(1999)
VLSI Digest of Technical Papers
, pp. 77-78
-
-
Irie, K.1
Kusayanagi, N.2
Kawachi, T.3
Nishibu, T.4
Matsumori, Y.5
-
69
-
-
2442664443
-
A 15 b 20 MS/s CMOS Pipelined ADC with Digital Background Calibration
-
H.-C. Liu, Z.-M. Lee, and J.-T. Wu, "A 15 b 20 MS/s CMOS Pipelined ADC with Digital Background Calibration," ISSCC Digest of Technical Papers, vol. 47, pp. 454-455, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 454-455
-
-
Liu, H.-C.1
Lee, Z.-M.2
Wu, J.-T.3
-
70
-
-
0032308622
-
A single-ended 12-bit 20 MSample/s self-calibrating pipeline A/D converter
-
I. Opris, L. Lewicki, and B. Wong, "A single-ended 12-bit 20 MSample/s self-calibrating pipeline A/D converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1898-1903, 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 1898-1903
-
-
Opris, I.1
Lewicki, L.2
Wong, B.3
-
71
-
-
0032316909
-
A continuously calibrated 12-b 10-MS/s, 3.3-V A/D converter
-
J. Ingino and B. Wooley, "A continuously calibrated 12-b 10-MS/s, 3.3-V A/D converter," IEEE J. Solid-State Circuits, vol. 33, pp. 1920-1931, 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 1920-1931
-
-
Ingino, J.1
Wooley, B.2
-
72
-
-
0036565022
-
Oversampled pipeline A/D converters with mismatch shaping
-
A. Shabra and H.-S. Lee, "Oversampled pipeline A/D converters with mismatch shaping," IEEE J. Solid-State Circuits, vol. 37, pp. 566-578, 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 566-578
-
-
Shabra, A.1
Lee, H.-S.2
-
73
-
-
0034428841
-
A 14 b 20 MSample/s CMOS pipelined ADC
-
H.-S. Chen, K. Bacrania, and B.-S. Song, "A 14 b 20 MSample/s CMOS pipelined ADC," ISSCC Digest of Technical Papers, pp. 46-47, 2000.
-
(2000)
ISSCC Digest of Technical Papers
, pp. 46-47
-
-
Chen, H.-S.1
Bacrania, K.2
Song, B.-S.3
-
74
-
-
0033879028
-
A pipeline A/D converter architecture with low DNL
-
I. Opris, B. Wong, and S. Chin, "A pipeline A/D converter architecture with low DNL," IEEE J. Solid-State Circuits, vol. 35, pp. 281-285, 2000.
-
(2000)
IEEE J. Solid-State Circuits
, vol.35
, pp. 281-285
-
-
Opris, I.1
Wong, B.2
Chin, S.3
-
75
-
-
2442676922
-
A 96 dB SFDR 50 MS/s Digitally Enhanced CMOS Pipeline A/D Converter
-
K. Nair and R. Harjani, "A 96 dB SFDR 50 MS/s Digitally Enhanced CMOS Pipeline A/D Converter," ISSCC Digest of Technical Papers, vol. 47, pp. 456-457, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 456-457
-
-
Nair, K.1
Harjani, R.2
-
76
-
-
2442657679
-
A 150 MS/s 8 b 71 mW Time-Interleaved ADC in 0.18 m CMOS
-
S. Limotyrakis, S. Kulchycki, D. Su, and B. Wooley, "A 150 MS/s 8 b 71 mW Time-Interleaved ADC in 0.18 m CMOS," ISSCC Digest of Technical Papers, vol. 47, pp. 258-259, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 258-259
-
-
Limotyrakis, S.1
Kulchycki, S.2
Su, D.3
Wooley, B.4
-
77
-
-
2442688304
-
A 1.8 v 14 b 10 MS/s Pipelined ADC in 0.18 m CMOS with 99 dB SFDR
-
Y. Chiu, P. Gray, and B. Nikolic, "A 1.8 V 14 b 10 MS/s Pipelined ADC in 0.18 m CMOS with 99 dB SFDR," ISSCC Digest of Technical Papers, vol. 47, pp. 458-459, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 458-459
-
-
Chiu, Y.1
Gray, P.2
Nikolic, B.3
-
78
-
-
2442656950
-
A digitally enhanced 1.8 v 15 b 40 MS/s CMOS pipelined ADC
-
E. Siragusa and I. Galton, "A Digitally Enhanced 1.8 V 15 b 40 MS/s CMOS Pipelined ADC," ISSCC Digest of Technical Papers, vol. 47, pp. 452-453, 2004.
-
(2004)
ISSCC Digest of Technical Papers
, vol.47
, pp. 452-453
-
-
Siragusa, E.1
Galton, I.2
-
79
-
-
0033682471
-
A 12 b 105 MSample/s, 850 mW analog to digital converter
-
C. Michalski, "A 12 b 105 MSample/s, 850 mW analog to digital converter," VLSI Digest of Technical Papers, pp. 208-211, 2000.
-
(2000)
VLSI Digest of Technical Papers
, pp. 208-211
-
-
Michalski, C.1
-
80
-
-
0037817786
-
A 0.5-V 1-μ W successive approximation ADC
-
J. Sauerbrey, D. Schmitt-Landsiedel, and R. Thewes, "A 0.5-V 1-μ W successive approximation ADC," IEEE J. Solid-State Circuits, vol. 38, pp. 1261-1265, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 1261-1265
-
-
Sauerbrey, J.1
Schmitt-Landsiedel, D.2
Thewes, R.3
-
81
-
-
0037480686
-
An ultralow-energy ADC for smart dust
-
M. Scott, B. Boser, and K. Pister, "An ultralow-energy ADC for smart dust," IEEE J. Solid-State Circuits, vol. 38, pp. 1123-1129, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 1123-1129
-
-
Scott, M.1
Boser, B.2
Pister, K.3
-
82
-
-
0038380412
-
Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue
-
E. Blecker, T. McDonald, O. Erdogan, P. Hurst, and S. Lewis, "Digital background calibration of an algorithmic analog-to-digital converter using a simplified queue," IEEE J. Solid-State Circuits, vol. 38, pp. 1059-1062, 2003.
-
(2003)
IEEE J. Solid-State Circuits
, vol.38
, pp. 1059-1062
-
-
Blecker, E.1
McDonald, T.2
Erdogan, O.3
Hurst, P.4
Lewis, S.5
-
83
-
-
0035247571
-
A 13.5-b 1.2-V micropower extended counting A/D converter
-
P. Rombouts, W. de Bilde, and L. Weyten, "A 13.5-b 1.2-V micropower extended counting A/D converter," IEEE J. Solid-State Circuits, vol. 36, pp. 176-183, 2001.
-
(2001)
IEEE J. Solid-State Circuits
, vol.36
, pp. 176-183
-
-
Rombouts, P.1
De Bilde, W.2
Weyten, L.3
-
84
-
-
18544399632
-
A 12-b digital-background-calibrated algorithmic ADC with-90-dB THD
-
O. Erdogan, P. Hurst, and S. Lewis, "A 12-b digital-background- calibrated algorithmic ADC with-90-dB THD," IEEE J. Solid-State Circuits, vol. 34, pp. 1812-1820, 1999.
-
(1999)
IEEE J. Solid-State Circuits
, vol.34
, pp. 1812-1820
-
-
Erdogan, O.1
Hurst, P.2
Lewis, S.3
-
85
-
-
0025538336
-
A 10-b 50-MHz CMOS D/A Converter with 75 Buffer
-
M. Pelgrom, "A 10-b 50-MHz CMOS D/A Converter with 75 Buffer," IEEE J. Solid-State Circuits, vol. 25, pp. 1347-1352, 19910.
-
IEEE J. Solid-State Circuits
, vol.25
, Issue.1991
, pp. 1347-1352
-
-
Pelgrom, M.1
-
86
-
-
0037954364
-
Design and characterization of a high-precision resistor ladder test structure
-
H. P. Tuinhout, G. Hoogzaad, M. Vertregt, R. L. J. Roovers, and C. Erd-mann, "Design and characterization of a high-precision resistor ladder test structure," IEEE Transactions on Semiconductor Manufacturing, vol. 16, pp. 187-193, 2003.
-
(2003)
IEEE Transactions on Semiconductor Manufacturing
, vol.16
, pp. 187-193
-
-
Tuinhout, H.P.1
Hoogzaad, G.2
Vertregt, M.3
Roovers, R.L.J.4
Erd-Mann, C.5
-
88
-
-
0024610903
-
A 10-bit 20-MHz two-step parallel A/D converter with internal S/H
-
T. Shimizu, M. Hotta, K. Maio, and S. Ueda, "A 10-bit 20-MHz two-step parallel A/D converter with internal S/H," IEEE J. Solid-State Circuits, vol. 24, pp. 13-20, 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 13-20
-
-
Shimizu, T.1
Hotta, M.2
Maio, K.3
Ueda, S.4
-
90
-
-
0027867460
-
A 10-b, 75-MHz two-stage pipelined bipolar A/D converter
-
W. Colleran and A. Abidi, "A 10-b, 75-MHz two-stage pipelined bipolar A/D converter," IEEE J. Solid-State Circuits, vol. 28, pp. 1187-1199, 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 1187-1199
-
-
Colleran, W.1
Abidi, A.2
-
91
-
-
0023326938
-
Monotonic dual-ladder A/D conversion
-
P. Grant and K. Smith, "Monotonic dual-ladder A/D conversion," IEEE J. Solid-State Circuits, vol. 22, pp. 295-297, 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, pp. 295-297
-
-
Grant, P.1
Smith, K.2
-
92
-
-
0024909871
-
A 12-bit 500-ns subranging ADC
-
M. Kolluri, "A 12-bit 500-ns subranging ADC," IEEE J. Solid-State Circuits, vol. 24, pp. 1498-1506, 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 1498-1506
-
-
Kolluri, M.1
-
93
-
-
0016592668
-
A percision trim technique for monolithic analog circuits
-
G. Erdi, "A percision trim technique for monolithic analog circuits," IEEE J. Solid-State Circuits, vol. 10, pp. 412-416, 1975.
-
(1975)
IEEE J. Solid-State Circuits
, vol.10
, pp. 412-416
-
-
Erdi, G.1
-
94
-
-
0030082854
-
A low-power 1 MHz. 25 mW 12-bit time-interleaved analog-to-digital converter
-
M. Mayes, S. Chin, and L. Stoian, "A low-power 1 MHz. 25 mW 12-bit time-interleaved analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 31, pp. 169-178, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 169-178
-
-
Mayes, M.1
Chin, S.2
Stoian, L.3
-
95
-
-
0031102975
-
A 10-b, 100-MS/s CMOS A/D converter
-
K. Kim, N. Kusayanagi, and A. Abidi, "A 10-b, 100-MS/s CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 32, pp. 302-311, 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 302-311
-
-
Kim, K.1
Kusayanagi, N.2
Abidi, A.3
-
96
-
-
0029753410
-
A 14-b, 2.5 MSps pipelined ADC with on-chip EPROM
-
D. Mercer, "A 14-b, 2.5 MSps pipelined ADC with on-chip EPROM," IEEE J. Solid-State Circuits, vol. 31, pp. 70-76, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 70-76
-
-
Mercer, D.1
-
97
-
-
0021616937
-
A self-calibrating 15 bit CMOS A/D converter
-
H.-S. Lee, D. Hodges, and P. Gray, "A self-calibrating 15 bit CMOS A/D converter," IEEE J. Solid-State Circuits, vol. 19, pp. 813-819, 1984.
-
(1984)
IEEE J. Solid-State Circuits
, vol.19
, pp. 813-819
-
-
Lee, H.-S.1
Hodges, D.2
Gray, P.3
-
98
-
-
0026999467
-
Digital-domain calibration of multistep analog-to-digital converters
-
S.-H. Lee and B.-S. Song, "Digital-domain calibration of multistep analog-to-digital converters," IEEE J. Solid-State Circuits, vol. 27, pp. 1679-1688, 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1679-1688
-
-
Lee, S.-H.1
Song, B.-S.2
-
99
-
-
0027853599
-
A 15-b 1-MSample/s digitally self-calibrated pipeline ADC
-
A. Karanicolas, H.-S. Lee, and K. Bacrania, "A 15-b 1-MSample/s digitally self-calibrated pipeline ADC," IEEE J. Solid-State Circuits, vol. 28, pp. 1207-1215, 1993.
-
(1993)
IEEE J. Solid-State Circuits
, vol.28
, pp. 1207-1215
-
-
Karanicolas, A.1
Lee, H.-S.2
Bacrania, K.3
-
100
-
-
0028417146
-
A 12-b 600 k/s digitally self-calibrated pipelined algorithmic ADC
-
H.-S. Lee, "A 12-b 600 k/s digitally self-calibrated pipelined algorithmic ADC," IEEE J. Solid-State Circuits, vol. 29, pp. 509-515, 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 509-515
-
-
Lee, H.-S.1
-
101
-
-
0029293925
-
A 13-b 10-MSample/s ADC digitally calibrated with oversampling delta-sigma converter
-
T.-H. Shu, B.-S. Song, and K. Bacrania, "A 13-b 10-MSample/s ADC digitally calibrated with oversampling delta-sigma converter," IEEE J. Solid-State Circuits, vol. 30, pp. 443-452, 1995.
-
(1995)
IEEE J. Solid-State Circuits
, vol.30
, pp. 443-452
-
-
Shu, T.-H.1
Song, B.-S.2
Bacrania, K.3
-
102
-
-
0036612580
-
A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter
-
S.-Y. Chuang and T. Sculley, "A digitally self-calibrating 14-bit 10-MHz CMOS pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 37, pp. 674-683, 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 674-683
-
-
Chuang, S.-Y.1
Sculley, T.2
-
103
-
-
0026141224
-
A 13-b 2.5-MHz self-calibrated pipelined A/D convertre in 3-μ m CMOS
-
Y.-M. Lin, B. Kim, and P. Gray, "A 13-b 2.5-MHz self-calibrated pipelined A/D convertre in 3-μ m CMOS," IEEE J. Solid-State Circuits, vol. 26, pp. 628-636, 1991.
-
(1991)
IEEE J. Solid-State Circuits
, vol.26
, pp. 628-636
-
-
Lin, Y.-M.1
Kim, B.2
Gray, P.3
-
104
-
-
0026996006
-
Design techniques for high-speed high-resolution comparators
-
B. Razavi and B. Wooley, "Design techniques for high-speed high-resolution comparators," IEEE J. Solid-State Circuits, vol. 27, pp. 1916-1926, 1992.
-
(1992)
IEEE J. Solid-State Circuits
, vol.27
, pp. 1916-1926
-
-
Razavi, B.1
Wooley, B.2
-
105
-
-
0024122160
-
A 12-bit 1-MSample/s capacitor error-averaging pipelined A/D converter
-
B.-S. Song, M. Tompsett, and K. Lakshmikumar, "A 12-bit 1-MSample/s capacitor error-averaging pipelined A/D converter," IEEE J. Solid-State Circuits, vol. 23, pp. 1324-1333, 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 1324-1333
-
-
Song, B.-S.1
Tompsett, M.2
Lakshmikumar, K.3
-
106
-
-
0023326939
-
A versatile building block: The CMOS differential difference amplifier
-
E. Sackinger and W. Guggenbuhl, "A versatile building block: the CMOS differential difference amplifier," IEEE J. Solid-State Circuits, vol. 22, pp. 287-294, 1987.
-
(1987)
IEEE J. Solid-State Circuits
, vol.22
, pp. 287-294
-
-
Sackinger, E.1
Guggenbuhl, W.2
-
107
-
-
0032308947
-
An analog background calibration technique for time interleaved analog to digital converters
-
K. Dyer, D. Fu, S. Lewis, and P. Hurst, "An analog background calibration technique for time interleaved analog to digital converters," IEEE J. Solid-State Circuits, vol. 33, pp. 1912-1919, 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 1912-1919
-
-
Dyer, K.1
Fu, D.2
Lewis, S.3
Hurst, P.4
-
108
-
-
0003105399
-
A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique
-
K. Yoon, S. Park, and W. Kim, "A 6 b 500 MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique," ISSCC Digest of Technical Papers, pp. 326-327, 1999.
-
(1999)
ISSCC Digest of Technical Papers
, pp. 326-327
-
-
Yoon, K.1
Park, S.2
Kim, W.3
-
109
-
-
0031359733
-
A 15-b, 5-MSample/s low-spurious CMOS ADC
-
S.-U. Kwak, H.-S. Lee, and K. Bacrania, "A 15-b, 5-MSample/s low-spurious CMOS ADC," IEEE J. Solid-State Circuits, vol. 32, pp. 1866-1875, 1997.
-
(1997)
IEEE J. Solid-State Circuits
, vol.32
, pp. 1866-1875
-
-
Kwak, S.-U.1
Lee, H.-S.2
Bacrania, K.3
-
110
-
-
0030414371
-
A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC
-
P. Yu and H.-S. Lee, "A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC," IEEE J. Solid-State Circuits, vol. 31, pp. 1854-1861, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1854-1861
-
-
Yu, P.1
Lee, H.-S.2
-
111
-
-
0035063625
-
A 14b 40MSample/s pipelined ADC with DFCA
-
P. Yu, S. Shehata, A. Joharapurkar, P. Chugh, A. Bugeja, X. Du, S.-U. Kwak, Y. Panantonopoulous, and T. Kuyel, "A 14b 40MSample/s pipelined ADC with DFCA," ISSCC Digest of Technical Papers, pp. 136-137, 2001.
-
(2001)
ISSCC Digest of Technical Papers
, pp. 136-137
-
-
Yu, P.1
Shehata, S.2
Joharapurkar, A.3
Chugh, P.4
Bugeja, A.5
Du, X.6
Kwak, S.-U.7
Panantonopoulous, Y.8
Kuyel, T.9
-
112
-
-
0032313025
-
A digital background calibration technique for time interleaved analog to digital converters
-
D. Fu, K. Dyer, S. Lewis, and P. Hurst, "A digital background calibration technique for time interleaved analog to digital converters," IEEE J. Solid-State Circuits, vol. 33, pp. 1904-1911, 1998.
-
(1998)
IEEE J. Solid-State Circuits
, vol.33
, pp. 1904-1911
-
-
Fu, D.1
Dyer, K.2
Lewis, S.3
Hurst, P.4
-
113
-
-
0033893576
-
Digital cancellation of D/A converter noise in pipelined A/D converters
-
I. Galton, "Digital Cancellation of D/A Converter Noise in Pipelined A/D Converters," IEEE Transaction on Circuits and Systems, vol. 47, pp. 185-196, 2000.
-
(2000)
IEEE Transaction on Circuits and Systems
, vol.47
, pp. 185-196
-
-
Galton, I.1
-
115
-
-
0036565022
-
Oversampled pipeline A/D converters with mismatch shaping
-
S.M. Yamal, D. Fu, N. C.-J. Chang, P. Hurst, and S. Lewis, "Oversampled pipeline A/D converters with mismatch shaping," IEEE J. Solid-State Circuits, vol. 37, pp. 566-578, 2002.
-
(2002)
IEEE J. Solid-State Circuits
, vol.37
, pp. 566-578
-
-
Yamal, S.M.1
Fu, D.2
Chang, N.C.-J.3
Hurst, P.4
Lewis, S.5
-
117
-
-
0024648085
-
A 10-bit 5-Msample/s CMOS two-step flash ADC
-
J. Doernberg, P. Gray, and D. Hodges, "A 10-bit 5-Msample/s CMOS two-step flash ADC," IEEE J. Solid-State Circuits, vol. 24, pp. 241-249, 1989.
-
(1989)
IEEE J. Solid-State Circuits
, vol.24
, pp. 241-249
-
-
Doernberg, J.1
Gray, P.2
Hodges, D.3
-
118
-
-
0016334230
-
A complete monolithic sample/hold amplifier
-
K. Stafford, P. Gary, and R. Blanchard, "A complete monolithic sample/hold amplifier," IEEE J. Solid-State Circuits, vol. 9, pp. 381-387, 1974.
-
(1974)
IEEE J. Solid-State Circuits
, vol.9
, pp. 381-387
-
-
Stafford, K.1
Gary, P.2
Blanchard, R.3
-
119
-
-
0035397706
-
Characterization of Poly-silicon Resistors in Sub-0.25μ m CMOS ULSI Applications
-
W. Liu, K.-B. Thei, H.-M. Chuang, K.-W. Lin, C.-C. Cheng, Y.-S. Ho, C.-W. Su, S.-C. Wong, C.-H. Lin, and C. Diaz, "Characterization of Poly-silicon Resistors in Sub-0.25μ m CMOS ULSI Applications," IEEE Electron Device Letters, vol. 22, pp. 318-320, 2001.
-
(2001)
IEEE Electron Device Letters
, vol.22
, pp. 318-320
-
-
Liu, W.1
Thei, K.-B.2
Chuang, H.-M.3
Lin, K.-W.4
Cheng, C.-C.5
Ho, Y.-S.6
Su, C.-W.7
Wong, S.-C.8
Lin, C.-H.9
Diaz, C.10
-
120
-
-
0030195073
-
CMOS low distortion high-frequency variable-gain amplifier
-
J. Rijns, "CMOS low distortion high-frequency variable-gain amplifier," IEEE J. Solid-State Circuits, vol. 31, pp. 1029-1035, 1996.
-
(1996)
IEEE J. Solid-State Circuits
, vol.31
, pp. 1029-1035
-
-
Rijns, J.1
-
121
-
-
0028419251
-
A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter
-
T. Miki, H. Kouno, Y. Kinoshita, T. Igarashi, and K. Okada, "A 10-b 50 MS/s 500-mW A/D converter using a differential-voltage subconverter," IEEE J. Solid-State Circuits, vol. 29, pp. 516-522, 1994.
-
(1994)
IEEE J. Solid-State Circuits
, vol.29
, pp. 516-522
-
-
Miki, T.1
Kouno, H.2
Kinoshita, Y.3
Igarashi, T.4
Okada, K.5
-
122
-
-
0019265826
-
Time interleaved converter arrays
-
W. Black and D. Hodges, "Time interleaved converter arrays," IEEE J. Solid-State Circuits, vol. 15, pp. 1022-1029, 1980.
-
(1980)
IEEE J. Solid-State Circuits
, vol.15
, pp. 1022-1029
-
-
Black, W.1
Hodges, D.2
-
123
-
-
84893807297
-
A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μ m CMOS
-
A. Zjajo, H. van der Ploeg, and M. Vertregt, "A 1.8V 100mW 12-bits 80Msample/s two-step ADC in 0.18-μ m CMOS," Proceedings of ESSIRC, pp. 241-244, 2003.
-
(2003)
Proceedings of ESSIRC
, pp. 241-244
-
-
Zjajo, A.1
Ploeg Der H.Van2
Vertregt, M.3
-
124
-
-
0024123362
-
An 8-bit 100-MHz full-Nyquist analog-to-digital converter
-
R. J. van de Plassche and P. Baltus, "An 8-bit 100-MHz full-Nyquist analog-to-digital converter," IEEE J. Solid-State Circuits, vol. 23, pp. 1334-1344, 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.23
, pp. 1334-1344
-
-
Plassche De Van, R.J.1
Baltus, P.2
-
125
-
-
0022862503
-
An 80-MHz 8-bit CMOS D/A Converter
-
T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, "An 80-MHz 8-bit CMOS D/A Converter," IEEE J. Solid-State Circuits, vol. 21, pp. 983-988, 1986.
-
(1986)
IEEE J. Solid-State Circuits
, vol.21
, pp. 983-988
-
-
Miki, T.1
Nakamura, Y.2
Nakaya, M.3
Asai, S.4
Akasaka, Y.5
Horiba, Y.6
-
126
-
-
0141958020
-
A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications
-
S.-B. You, J.-W. Kim, and S. Kim, "A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications," IEEE Transactions on Consumer Electronics, vol. 49, pp. 647-652, 2003.
-
(2003)
IEEE Transactions on Consumer Electronics
, vol.49
, pp. 647-652
-
-
You, S.-B.1
Kim, J.-W.2
Kim, S.3
-
127
-
-
84891980508
-
-
Redundancy can be used in all types of converters where a selection has to be made for the following step These are the pipe-lined, two-step and successive approximation (SAR) architectures, as explained later
-
Redundancy can be used in all types of converters where a selection has to be made for the following step. These are the pipe-lined, two-step and successive approximation (SAR) architectures, as explained later.
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-
-
-
128
-
-
84891973290
-
-
Another option could be to calibrate the gain of a single residue system instead of the offset in a dual-residue system However, in this book offset calibration is chosen over gain calibration since offset can be measured and compensated more easily because it is a DC effect
-
Another option could be to calibrate the gain of a single residue system instead of the offset in a dual-residue system. However, in this book offset calibration is chosen over gain calibration since offset can be measured and compensated more easily because it is a DC effect
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-
-
-
129
-
-
84891982178
-
-
A similar offset detection method has been published later than [58] in [115]
-
A similar offset detection method has been published later than [58] in [115].
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