A 10b 150MS/s 123mW 0.18μm CMOS pipelined ADC

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2003, Pages

  Yoo, Sang Min ^a   Park, Jong Bum ^b   Yang, Hee Suk ^b   Bae, Hyuen Hee ^b   Moon, Kyoung Ho ^a   Park, Ho Jin ^a   Lee, Seung Hoon ^b   Kim, Jae Hwui ^a  

^a SAMSUNG Electronics   (South Korea)

^b Sogang University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BIT ERROR RATE; BUFFER AMPLIFIERS; INTEGRATED CIRCUIT MANUFACTURE; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS; SIGNAL NOISE MEASUREMENT; SIGNAL TO NOISE RATIO; TEMPERATURE;

OFF CHIP VOLTAGE REFERENCES; ON CHIP VOLTAGE REFERENCES; SAMPLE AND HOLD AMPLIFIERS;

CMOS INTEGRATED CIRCUITS;

EID: 0038306334     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. S. M. Jamal, D. Fu, P. Hurst, and S. Lewis, "A 10b 120MSample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration," ISSCC Dig. Tech. Papers, pp. 172-173, Feb. 2002.
2. L. Sumanen et al., "A 10-bit 200-MS/s CMOS parallel pipeline A/D converter," IEEE JSSC, vol. 36, no. 7, pp. 1048-1055, July 2001.
3. S. M. Yoo, T. H. Oh, J. W. Moon, S. H. Lee, and U. K. Moon, "A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR," Proc. CICC, pp. 441-444, May, 2002.
4. A. Abo and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipelined Analog-to-Digital Converter," IEEE JSSC, vol. 34, no. 5, pp. 599-606, May 1999.
5. L. Singer, S. Ho, M. Timko, and D. Kelly, "A 12b 65MSample/s CMOS ADC with 82dB SFDR at 120MHz," ISSCC Dig. Tech. Papers, pp. 38-39, Feb. 2000.
6. 2 49mW 0.18μm CMOS ADC with On-chip Current/Voltage References," Proc. ESSCIRC, Sep. 2002.