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Volumn 36, Issue 1, 2001, Pages 122-128

8-bit 10 MS/s folding and interpolating ADC using the continuous-time auto-zero technique

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPARATOR CIRCUITS; DIFFERENTIAL AMPLIFIERS; INTERPOLATION; SIGNAL DISTORTION; SIGNAL TO NOISE RATIO;

EID: 0035117766     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.896236     Document Type: Article
Times cited : (16)

References (12)
  • 1
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    • Dec
    • M. P. Flynn and B. Sheahan, "A 400-Msample/s 6-b CMOS folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 33, pp. 1932-1938, Dec. 1998.
    • (1998) IEEE J. Solid-state Circuits , vol.33 , pp. 1932-1938
    • Flynn, M.P.1    Sheahan, B.2
  • 2
    • 0031378861 scopus 로고    scopus 로고
    • A 12-b 60-Msamples/s cascaded folding and interpolating ADC
    • Dec
    • P. Vorenkamp and R. Roovers, "A 12-b 60-Msamples/s cascaded folding and interpolating ADC," IEEE J. Solid-State Circuits, vol. 32, pp. 1876-1886, Dec. 1997.
    • (1997) IEEE J. Solid-state Circuits , vol.32 , pp. 1876-1886
    • Vorenkamp, P.1    Roovers, R.2
  • 4
    • 0030241345 scopus 로고    scopus 로고
    • CMOS folding A/D converters with current-mode interpolation
    • Sept
    • M. P. Flynn and D. J. Allstot, "CMOS folding A/D converters with current-mode interpolation," IEEE J. Solid-State Circuits, vol. 31, pp. 1248-1257, Sept. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 1248-1257
    • Flynn, M.P.1    Allstot, D.J.2
  • 5
    • 0029510025 scopus 로고
    • A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter
    • Dec
    • B. Naula and A. G. W. Venes, "A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter," IEEE J. Solid-State Circuits, vol. 30, pp. 1302-1308, Dec. 1995.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , pp. 1302-1308
    • Naula, B.1    Venes, A.G.W.2
  • 6
    • 0030411456 scopus 로고    scopus 로고
    • An 80-MHz 80mW 8-b CMOS folding A/D converter with distributed track- and-hold preprocessing
    • Dec
    • A. G. W. Venes and R. J. van de Plassche, "An 80-MHz 80mW 8-b CMOS folding A/D converter with distributed track- and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 1846-1853
    • Venes, A.G.W.1    Van De Plassche, R.J.2
  • 7
    • 0343103726 scopus 로고    scopus 로고
    • Power and scaling rules of CMOS high-speed A/D converters
    • Norwood, MA: Kluwer
    • A. G. W. Venes and R. J. van de Plassche, "Power and scaling rules of CMOS high-speed A/D converters," in Analog Circuit Design. Norwood, MA: Kluwer, 1997, pp. 25-48.
    • (1997) Analog Circuit Design , pp. 25-48
    • Venes, A.G.W.1    Van De Plassche, R.J.2
  • 8
    • 0030290680 scopus 로고    scopus 로고
    • Low-jitter process-independent DLL and PLL based on self-biased techniques
    • Nov
    • J. G. Maneatis, "Low-jitter process-independent DLL and PLL based on self-biased techniques," IEEE J. Solid-State Circuits, vol. 31, pp. 1723-1727, Nov. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 1723-1727
    • Maneatis, J.G.1
  • 9
    • 0032316106 scopus 로고    scopus 로고
    • A CMOS 6-b 400-Msample/s ADC with error correction
    • Dec
    • S. Tsukamoto, W. Schofield, and T. Endo, "A CMOS 6-b 400-Msample/s ADC with error correction," IEEE J. Solid-State Circuits, vol. 33, pp. 1939-1947, Dec. 1998.
    • (1998) IEEE J. Solid-state Circuits , vol.33 , pp. 1939-1947
    • Tsukamoto, S.1    Schofield, W.2    Endo, T.3
  • 11
    • 0030288231 scopus 로고    scopus 로고
    • A CMOS 6-b 200MSample/s 3 v-supply A/D converter for a PRML read channel LSI
    • S. Tsukamoto et al., "A CMOS 6-b 200MSample/s 3 V-supply A/D converter for a PRML read channel LSI," IEEE J. Solid-State Circuits, vol. 31, pp. 1831-1836, Nov. 1996.
    • (1996) IEEE J. Solid-state Circuits , vol.31 , pp. 1831-1836
    • Tsukamoto, S.1
  • 12
    • 0003105399 scopus 로고    scopus 로고
    • A 6-b 500-MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique
    • WA 18.6
    • K. Yoon et al., "A 6-b 500-MSample/s CMOS flash ADC with a background interpolated auto-zeroing technique," in Proc. ISSCC, 1999, WA 18.6, pp. 326-327.
    • (1999) Proc. ISSCC , pp. 326-327
    • Yoon, K.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.