An embedded 0.8 V/480 μW 6B/22 MHz flash ADC in 0.13-μm digital CMOS process using a nonlinear double interpolation technique

IEEE Journal of Solid-State Circuits

Volumn 37, Issue 12, 2002, Pages 1610-1617

  Lin, Jerry ^a   Haroun, Baher ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

ADC; Double interpolation; Interpolation; Low power; Low voltage

Indexed keywords

ELECTRIC CONVERTERS; ELECTRIC POTENTIAL; INTERPOLATION; NONLINEAR SYSTEMS; RESISTORS; WIRELESS TELECOMMUNICATION SYSTEMS;

BASEBAND CONVERTERS;

CMOS INTEGRATED CIRCUITS;

EID: 0036912822     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2002.804333     Document Type: Conference Paper

References (22)

1. K. Bult, "Broadband communication circuits in pure digital deep submicron CMOS," in Proc. ISSCC, 1999, pp. 76-77.
2. D.A. Johns and K. Martin, Analog Integrated Circuit Design. New York: Wiley, 1997, pp. 517-523.
3. F. Goodenough, "Interpolators put 10-bit 75-MHz A/D converters on 8-bit digital process," Electron. Design, pp. 29-30, Dec. 14, 1989.
4. M. Steyaert, R. Roovers, and J. Craninckx, "A 100 MHz 8 bit CMOS interpolating A/D converter," in Proc. CICC, 1993, pp. 28.1.1-28.1.4.
5. R.E.J. van de Grift, I.W.J.M. Rutten, and M. van de Veen, "An 8-bit video ADC incorporating folding and interpolation techniques," IEEE J. Solid-State Circuits, vol. SC-22, pp. 944-953 Dec. 1987.
6. J. van Valburg and R.J. van de Plassche, "An 8-b 650-MHz folding ADC," IEEE J. Solid-State Circuits, vol. 27, pp. 1662-1666, Dec. 1992.
7. A.G.W. Venes and R.J. van-de-Plassche, "An 80-MHz, 80-mW, 8-b CMOS folding A/D converter with distributed track-and-hold preprocessing," IEEE J. Solid-State Circuits, vol. 31, pp. 1846-1853, Dec. 1996.
8. B. Razavi, "Design of sample-and-hold amplifiers for high-speed low-voltage A/D converters," in Proc. CICC, 1997, pp. 59-66.
9. K. Nagaraj, D.A. Martin, M. Wolfe, R. Chattopadhyay, S. Pavan, J. Cancio, and T.R. Viswanathan, "A dual-mode 700-Msamples/s 6-bit 200-Msamples/s 7-bit A/D converter in a 0.25 μm digital CMOS process," IEEE J. Solid-State Circuits, vol. 35, pp. 1760-1768, Dec. 2000.
10. K. Bult and A. Buchwald, "An embedded 240-mW 10-b 50-MS/s CMOS ADC in 1-mm2," IEEE J. Solid-State Circuits, vol. 32, pp. 748-754, Dec. 1997.
11. B.-S. Song, M.F. Tompsett, and K.R. Lakshmikumar, "A 12-bit 1-Msample/s capacitor error-averaging pipelined A/D converter," IEEE Solid-State Circuits, vol. 23, pp. 1324-1333, Dec. 1988.
12. B. Razavi, "Data conversion system design," IEEE Process, p. 101, 1995.
13. R.H. Walden, "Analog-to-digital converter survey and analysis," IEEE J. Select. Areas Commun., vol. 17, pp. 96-101, Apr. 1999.
14. M. Choi and A.A. Abidi, "A 6 b 1.3 GSample/s A/D converter in 0.35 um CMOS," in Proc. ISSCC, vol. 438, 2001, pp. 126-127.
15. K. Vleugels, S. Rabii, and B.A. Wooley, "A 2.5 V broadband multi-bit Sigma-Delta modulator with 95 dB dynamic range," in Proc. ISSCC, 2001, pp. 50-51.
16. G. Geelen, "A 6 b 1.1 GSample/s CMOS A/D converter," in Proc. ISSCC, 2001, pp. 128-129.
17. T. Buyer and Q. Huang, "A 13.5 mW, 185 MSample/s Delta Sigma-modulator for UMTS/GSM dual-standard IF reception," in Proc. ISSCC, 2001, pp. 44-45.
18. K. Gulati and H.-S. Lee, "A low-power reconfigurable analog-to-digital converter," in Proc. ISSCC, 2001, pp. 54-55.
19. Y.-I. Park, S. Karthikeyan, F. Tsay, and E. Bartolome, "A 10 b 100 MSample/s CMOS pipelined ADC with 1.8 V power supply," in Proc. ISSCC, 2001, pp. 130-131.
20. D. Kelly, W. Yang, I. Mehr, M. Sayuk, and L. Singer, "A 3 V 340 mW 14 b 75 MSPS CMOS ADC with 85 dB SFDR at Nyquist," in Proc. ISSCC, 2001, pp. 134-135.
21. O. Oliaei, P. Clement, and P. Gorisse, "A 5 mW Sigma Delta modulator with 84 dB dynamic range for GSM/EDGE," in Proc. ISSCC, 2001, pp. 46-47.
22. D. Robertson, "Specifications and figures of merit for mixed-signal circuits - A guide to understanding where the numbers come from and what they mean," in ISSCC 2002 Tutorial, Feb. 3, 2002, p. 37.