A 14b 40Msample/s pipelined ADC with DFCA

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2001, Pages 136-137+439

  Yu, P C ^a   Shehata, S ^a   Joharapurkar, A ^a   Chugh, P ^a   Bugeja, A R ^a   Du, X ^a   Kwak, S U ^a   Papantonopoulous, Y ^a   Kuyel, T ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BANDWIDTH; CALIBRATION; CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; SIGNAL TO NOISE RATIO;

CAPACITOR MISMATCH; MATCH NOISE CANCELLATION (MNC);

CAPACITORS;

EID: 0035063625     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Digital cancellation of D/A converter noise in pipelined A/D converters
2. An 8b 80Msample/s pipelined ADC with background calibration
3. A continuously-calibrated 10Msample/s 12b 3.3V ADC
4. A 2.5V 12b 5Msample/s pipelined CMOS ADC