An efficent clustering algorithm for low power clock tree synthesis

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2007, Pages 181-188

  Shelar, Rupesh S ^a  

^a INTEL CORPORATION   (United States)

Author keywords

Clock tree synthesis; Clustering; Low power

Indexed keywords

BUFFER CIRCUITS; CAPACITANCE; CLUSTERING ALGORITHMS; CONSTRAINT THEORY; MICROPROCESSOR CHIPS; NANOELECTRONICS; TIMING CIRCUITS;

CLOCK TREE CAPACITANCE; CLOCK TREE SYNTHESIS; MINIMUM SPANNING TREE (MST);

INTERCONNECTION NETWORKS;

EID: 34748839686     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1231996.1232037     Document Type: Conference Paper

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