GDRouter: Interleaved global routing and detailed routing for ultimate routability

Proceedings - Design Automation Conference

Volumn , Issue , 2012, Pages 597-602

  Zhang, Yanheng ^a   Chu, Chris ^b  

^a CADENCE DESIGN SYSTEMS   (United States)

^b IOWA STATE UNIVERSITY   (United States)

Author keywords

physical design; routing; VLSI cad

Indexed keywords

DETAILED ROUTING; FAST IMPLEMENTATION; GLOBAL CAPACITY; GLOBAL ROUTERS; GLOBAL ROUTING; PHYSICAL DESIGN; ROUTABILITY; ROUTING; ROUTING PHASE; RUNTIME OVERHEADS; RUNTIMES; TEST CASE; VLSI CAD; VORONOI DIAGRAM METHOD;

ALGORITHMS; COMPUTER AIDED DESIGN;

ROUTING PROTOCOLS;

EID: 84863544142     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2228360.2228469     Document Type: Conference Paper

References (24)

1. Y.Xu, Y.Zhang, and C.Chu. FastRoute 4.0: Global router with efficient via minimization. In Proc. Asia and South Pacific Design Automation Conf., pages 576-581, 2009.
2. Y. Zhang and C. Chu. RegularRoute: An efficient detailed router with regular routing patterns. In Proc. ACM/SIGDA Intl. Symp. on Physical Design, pages 146-151, 2011.
3. ISPD98 global routing benchmarks. http://www.ece.ucsb.edu/~kastner/ labyrinth.
4. ISPD05 placement contest benchmarks. http://www.sigda.org/ispd2005/ contest.htm.
5. ISPD06 placement contest benchmarks. http://www.sigda.org/ispd2006/ contest.htm.
6. M. R. Garey and D. S. Johnson. Computers and Intractability: A Guide to the Theory of NP-Completeness. Freeman, NY, 1979.
7. ISPD07 global routing contest benchmarks. http://www.sigda.org/ispd2007/ contest.htm.
8. ISPD08 global routing contest benchmarks. http://www.sigda.org/ispd2008/ contest.htm.
9. K. Yuan M. Cho, K. Lu and D. Z. Pan. Boxrouter 2.0: Architecture and implementation of a hybrid and robust global router. In Proc. Intl. Conf. on Computer-Aided Design, pages 503-508, 2007.
10. P.-C. Wu J.-R. Gao and T.-C. Wang. A new global router for modern designs. In Proc. Asia and South Pacific Design Automation Conf., pages 232-237, 2008.
11. M. M. Ozdal and M. D.F. Wong. High-performance routing at the nanometer scale. In Proc. Intl. Conf. on Computer-Aided Design, pages 496-502, 2007.
12. Y. Zhang, Y. Xu, and C. Chu. FastRoute 3.0: A fast and high quality global router based on virtual capacity. In Proc. Intl. Conf. on Computer-Aided Design, pages 344-349, 2008.
13. IBM-Place 1.0 benchmark suites. http://er.cs.ucla.edu/benchmarks/ibm- place/.
14. M. Pan and C. Chu. Fastroute: A step to integrate global routing into placement. In Proc. Intl. Conf. on Computer-Aided Design, pages 464-471, 2006.
15. M.Pan and C.Chu. FastRoute 2.0: A high-quality and efficient global router. In Proc. Asia and South Pacific Design Automation Conf., pages 250-255, 2007.
16. S. Batterywala, N. Shenoy, W. Nicholls, and H. Zhou. Track assignment: A desirable intermediate step between global routing and detailed routing. In Proc. Intl. Conf. on Computer-Aided Design, pages 59-66, 2002.
17. H. Chen, S. Chou, S. Wang, and Y. Chang. Novel wire density driven full-chip routing for cmp variation control. In Proc. Intl. Conf. on Computer-Aided Design, pages 831-838, 2007.
18. M. de Berg, M. van Kreveld, M. Overmars, and O. Schwarzkoph. Computational Geometry: Algorithms and Applications. Springer, 1997.
19. E. Bozorgzadeh R. Kastner and M. Sarrafzadeh. Pattern routing: Use and theory for increasing predictability and avoiding coupling. IEEE Trans. on Computer-Aided Design and Integrated Circuits and Systems, 21(7):777-790, July 2002.
20. X.Yang, B.Choi, and M.Sarrafzadeh. Routability-driven white space allocation for fixed-die standard-cell placement. IEEE Trans. on Computer-Aided Design and Integrated Circuits and Systems, 22(4):410-419, April 2003.
21. N.Viswanathan, M.Pan, and C.Chu. FastPlace 3.0: A fast multilevel quadratic placement algorithm with placement congestion control. In Proc. Asia and South Pacific Design Automation Conf., pages 135-140, 2007.
22. Y. Zhang and C. Chu. CROP: Fast and effective congestion refinement of placement. In Proc. Intl. Conf. on Computer-Aided Design, pages 344-350, 2009.
23. J.Z. Yan and C. Chu. Handling complexities in modern large-scale mixed-size placement. In Proc. ACM/IEEE Design Automation Conf., pages 436-441, 2009.
24. J.Z. Yan and C. Chu. DeFer: defered decision making enabled fixed-outline floorplanner. In Proc. ACM/IEEE Design Automation Conf., pages 161-166, 2008.