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Volumn , Issue , 2005, Pages 216-220

The ISPD2005 placement contest and benchmark suite

Author keywords

Benchmarks; Physical design; VLSI Placement

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; INDUSTRIAL APPLICATIONS; INTEGRATED CIRCUIT LAYOUT; VLSI CIRCUITS;

EID: 29144447716     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1055137.1055182     Document Type: Conference Paper
Times cited : (117)

References (17)
  • 13
    • 0036575032 scopus 로고    scopus 로고
    • Toward CAD-IP reuse: The MARCO GSRC bookshelf of fundamental CAD algorithms
    • May
    • A.E. Caldwell, A. B. Kahng, I. L. Markov, "Toward CAD-IP Reuse: The MARCO GSRC Bookshelf of Fundamental CAD Algorithms," IEEE Design and Test, May 2002, pp. 72-81, http://vlsicad.eecs.umich.edu/BK/Slots/
    • (2002) IEEE Design and Test , pp. 72-81
    • Caldwell, A.E.1    Kahng, A.B.2    Markov, I.L.3
  • 14
    • 0029264395 scopus 로고
    • Efficient and effective placement for very large circuits
    • Mar.
    • W.-J. Sun and C. Sechen, "Efficient and Effective Placement for Very Large Circuits," IEEE Trans. Computer-Aided Design, vol. 14, pp. 349-359, Mar. 1995.
    • (1995) IEEE Trans. Computer-aided Design , vol.14 , pp. 349-359
    • Sun, W.-J.1    Sechen, C.2
  • 15
    • 2942639682 scopus 로고    scopus 로고
    • Fastplace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
    • N. Viswanathan and C. C.-N. Chu, "Fastplace: Efficient Analytical Placement Using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," in Proc. International Symposium on Physical Design, 2004, pp. 26-33.
    • (2004) Proc. International Symposium on Physical Design , pp. 26-33
    • Viswanathan, N.1    Chu, C.C.-N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.