Toward the integration of incremental physical synthesis optimizations

2009 International Symposium on VLSI Design, Automation and Test, VLSI-DAT '09

Volumn , Issue , 2009, Pages 23-26

  Nam, Gi Joon ^a   Papa, David ^a   Moffitt, Michael ^a   Alpert, Charles ^a  

^a IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ACCURATE TIMING; GATE SIZING; HIGH FREQUENCY HF; HIGH-PERFORMANCE DESIGN; INCREMENTAL OPTIMIZATION; INCREMENTAL PLACEMENT; MICROPROCESSOR DESIGNS; PHYSICAL SYNTHESIS; PICOSECONDS; STANDARD-CELL; SUB-CIRCUITS; TIMING MODELS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; GATES (TRANSISTOR); OPTIMIZATION; RAILROAD TUNNELS; TIME MEASUREMENT;

DESIGN;

EID: 77950684660     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/VDAT.2009.5158085     Document Type: Conference Paper

References (4)

1. C. J. Alpert et al., "Accurate Estimation of Global Buffer Delay within a Floorplan", IEEE Trans. on Computer-Aided Design, vol. 25, no. 6, pp. 1140-1146.
2. P. Cocchini, "Concurrent Flip-flop and Repeater Insertion for High Performance Integrated Circuits", in Proc. ICCAD, 2002, pp. 268-273.
3. M. Moffitt, D. Papa, Z. Li and C. Alpert, "Path Smoothing via Discrete Optimization", in Proc. DAC, 2008, pp. 724-727.
4. D. Papa, T. Luo, M. Moffitt, C. Sze, Z. Li, G.-J. Nam, C. Alpert and I. Markov, "RUMBLE: An Incremental Timing- Driven Physical Synthesis Optimization Algorithm", IEEE Trans. on Computer-Aided Design, vol. 27, no. 12, pp. 2156- 2168.