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Volumn 1, Issue , 2005, Pages 331-336

On structure and suboptimality in placement

Author keywords

[No Author keywords available]

Indexed keywords

GLOBAL PLACEMENTS; REGULAR STRUCTURE; RUNTIMES; SUBOPTIMALITY;

EID: 84861448654     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1120725.1120864     Document Type: Conference Paper
Times cited : (15)

References (22)
  • 7
    • 0031386317 scopus 로고    scopus 로고
    • Interconnect layout optimization under higher-' order RLC model
    • J. Cong and C.-K. Koh. Interconnect layout optimization under higher-' order RLC model. In Proc. Int. Conf on Computer Aided Design, pages 713-720, 1997.
    • (1997) Proc. Int. Conf on Computer Aided Design , pp. 713-720
    • Cong, J.1    Koh, C.-K.2
  • 8
  • 10
    • 84861450868 scopus 로고    scopus 로고
    • US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design
    • D. Hill. US patent 6,370,673: Method and system for high speed detailed placement of cells within an integrated circuit design, 2002.
    • (2002)
    • Hill, D.1
  • 12
    • 0031643951 scopus 로고    scopus 로고
    • Practical experiences with standard-cell based datapath design tools: Do we really need regular layouts?
    • P. Ienne and A. Griessing. Practical experiences with standard-cell based datapath design tools: do we really need regular layouts? In Proc. Design Automation Conf, pages 396-401, 1998.
    • (1998) Proc. Design Automation Conf , pp. 396-401
    • Ienne, P.1    Griessing, A.2
  • 13
    • 0028712930 scopus 로고
    • Low-cost single-layer clock trees with exact zero Elmore delay skew
    • A. B. Kahng and C.-W. A. Tsao. Low-cost single-layer clock trees with exact zero Elmore delay skew. In Proc. Int. Conf. on Computer Aided Design, pages 213-218, 1994.
    • (1994) Proc. Int. Conf. on Computer Aided Design , pp. 213-218
    • Kahng, A.B.1    Tsao, C.-W.A.2
  • 14
    • 2942682815 scopus 로고    scopus 로고
    • Implementation and extensibility of an analytic 'placer
    • A. B. Kahng and Q. Wang. Implementation and extensibility of an analytic 'placer. In Proc. Int. Symp. on Physical Design, pages 18-25, 2004.
    • (2004) Proc. Int. Symp. on Physical Design , pp. 18-25
    • Kahng, A.B.1    Wang, Q.2
  • 16
    • 26444479778 scopus 로고
    • Optimization by simulated annealing
    • May
    • S. Kirkpatrick, C. D. Gelatt, and M. P. Vecchi. Optimization by simulated annealing. Science, 220(4598):671-680, May 1983.
    • (1983) Science , vol.220 , Issue.4598 , pp. 671-680
    • Kirkpatrick, S.1    Gelatt, C.D.2    Vecchi, M.P.3
  • 20
    • 0029226969 scopus 로고
    • Timing driven placement for large standard cell circuits
    • W. Swartz and C. Sechen. Timing driven placement for large standard cell circuits. In Proc. Design Automation Conf, pages 211-215, 1995.
    • (1995) Proc. Design Automation Conf , pp. 211-215
    • Swartz, W.1    Sechen, C.2
  • 21
    • 2942639682 scopus 로고    scopus 로고
    • Fastplace: Efficient analytical placement using cell shifting, iterative local refi nement and a hybrid net model
    • N. Viswanathan and C. C.-N. Chu. Fastplace: Efficient analytical placement using cell shifting, iterative local refi nement and a hybrid net model. In Proc. Int. Symp. on Physical Design, pages 26-33, 2004.
    • (2004) Proc. Int. Symp. on Physical Design , pp. 26-33
    • Viswanathan, N.1    Chu, C.C.-N.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.