메뉴 건너뛰기




Volumn , Issue , 2012, Pages 121-128

Novel pulsed-latch replacement based on time borrowing and spiral clustering

Author keywords

Clock power; Pulsed latch; Pulsed register; Time borrowing

Indexed keywords

CLOCK GATING; CLUSTERING METHODS; HIGH-PERFORMANCE CIRCUITS; IC DESIGNS; POWER EFFICIENT; PULSED-LATCH; PULSED-REGISTER; TIME BORROWING; TIMING CONSTRAINTS;

EID: 84860243262     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2160916.2160944     Document Type: Conference Paper
Times cited : (6)

References (19)
  • 1
    • 34748839686 scopus 로고    scopus 로고
    • An efficent clustering algorithm for low power clock tree synthesis
    • DOI 10.1145/1231996.1232037, 1232037, Proceedings of ISPD'07: 2007 International Symposium on Physical Design
    • R. S. Shelar, "An efficient clustering algorithm for low power clock tree synthesis," in Proc. Int. Symp. on Physical Design (ISPD), Mar. 2007, pp. 181-188. (Pubitemid 47485401)
    • (2007) Proceedings of the International Symposium on Physical Design , pp. 181-188
    • Shelar, R.S.1
  • 4
    • 79851484870 scopus 로고    scopus 로고
    • Pulsed-latch circuits to push the envelope of ASIC design
    • Nov.
    • S. Paik and Y. Shin, "Pulsed-latch circuits to push the envelope of ASIC design," in Proc. Int'l SoC Design Conf. (ISOCC), pp. 150-153, Nov. 2010.
    • (2010) Proc. Int'l SoC Design Conf. (ISOCC) , pp. 150-153
    • Paik, S.1    Shin, Y.2
  • 5
    • 57849154404 scopus 로고    scopus 로고
    • Pulse width allocation with clock skew scheduling for optimizing pulsed-latchbased sequential circuits
    • Nov.
    • H. Lee, S. Paik, and Y. Shin, "Pulse width allocation with clock skew scheduling for optimizing pulsed-latchbased sequential circuits," in Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 224-229, Nov. 2008.
    • (2008) Proc. Int'l Conf. on Computer-Aided Design (ICCAD) , pp. 224-229
    • Lee, H.1    Paik, S.2    Shin, Y.3
  • 6
    • 76349110520 scopus 로고    scopus 로고
    • Retiming and time borrowing: Optimizing high-performance pulsed-latchbased circuits
    • Nov.
    • S. Lee, S. Paik, and Y. Shin, "Retiming and time borrowing: optimizing high-performance pulsed-latchbased circuits," in Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 375-380, Nov. 2009.
    • (2009) Proc. Int'l Conf. on Computer-Aided Design (ICCAD) , pp. 375-380
    • Lee, S.1    Paik, S.2    Shin, Y.3
  • 9
    • 77951240740 scopus 로고    scopus 로고
    • Pulse-latch approach reduces dynamic power
    • July
    • S. Shibatani and A. H.C. Li, "Pulse-latch approach reduces dynamic power," EE Times, July 2006.
    • (2006) EE Times
    • Shibatani, S.1    Li, A.H.C.2
  • 13
    • 84855808128 scopus 로고    scopus 로고
    • Implementation of pulsed latch and pulsed register circuits to minimize clocking power
    • Nov.
    • S. Paik, G.-J. Nam, and Y. Shin, "Implementation of pulsed latch and pulsed register circuits to minimize clocking power, " in Proc. Int'l Conf. on Computer-Aided Design (ICCAD), pp. 640-646, Nov. 2011.
    • (2011) Proc. Int'l Conf. on Computer-Aided Design (ICCAD) , pp. 640-646
    • Paik, S.1    Nam, G.-J.2    Shin, Y.3
  • 17
    • 78649499437 scopus 로고    scopus 로고
    • An effective gated clock tree design based on activity and register aware placement
    • Dec.
    • W. Shen, Y. Cai, X. Hong, and J. Hu, "An effective gated clock tree design based on activity and register aware placement," IEEE Trans. Very Large Scale Integration Systems (TVLSI), vol. 18, no. 12, Dec. 2010, pp. 1639-1648.
    • (2010) IEEE Trans. Very Large Scale Integration Systems (TVLSI) , vol.18 , Issue.12 , pp. 1639-1648
    • Shen, W.1    Cai, Y.2    Hong, X.3    Hu, J.4


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.