Implementation of pulsed-latch and pulsed-register circuits to minimize clocking power

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, ICCAD

Volumn , Issue , 2011, Pages 640-646

  Paik, Seungwhun ^a   Nam, Gi Joon ^b   Shin, Youngsoo ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

low clocking power; Pulsed latch; pulsed register

Indexed keywords

CLOCK PULSE; CLOCK ROUTING; CMOS TECHNOLOGY; FLIP-FLOP DESIGNS; ILP FORMULATION; INSERTION PROBLEMS; LOAD CONSTRAINTS; LOW CLOCKING POWER; MIGRATION PROCESS; PULSED-LATCH; PULSED-REGISTER; WIRE LENGTH;

CLUSTERING ALGORITHMS; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; HEURISTIC ALGORITHMS; INDUCTIVE LOGIC PROGRAMMING (ILP); PROBLEM SOLVING;

FLIP FLOP CIRCUITS;

EID: 84855808128     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2011.6105397     Document Type: Conference Paper

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