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Volumn 2005, Issue , 2005, Pages 891-898

Architecture and details of a high quality, large-scale analytical placer

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARKING; COMPUTATIONAL COMPLEXITY; COMPUTER ARCHITECTURE; CONSTRAINT THEORY; LAWS AND LEGISLATION; QUALITY ASSURANCE;

EID: 33745967691     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCAD.2005.1560188     Document Type: Conference Paper
Times cited : (90)

References (39)
  • 10
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    • Can recursive bisection alone produce routable placements?
    • _, "Can Recursive Bisection Alone Produce Routable Placements?" in Proc. ACM/IEEE Design Automation Conference, 2000, pp. 477-482.
    • (2000) Proc. ACM/IEEE Design Automation Conference , pp. 477-482
  • 17
    • 0019478261 scopus 로고
    • An efficient algorithm for the two-dimensional placement problem in electrical circuit layout
    • S. Goto, "An Efficient Algorithm for the Two-Dimensional Placement Problem in Electrical Circuit Layout," IEEE Transactions on Circuits and Systems, vol. 28(1), pp. 12-18, 1981.
    • (1981) IEEE Transactions on Circuits and Systems , vol.28 , Issue.1 , pp. 12-18
    • Goto, S.1
  • 18
    • 2942660384 scopus 로고    scopus 로고
    • Method and system for high speed detailed placement of cells within an integrated circuit design
    • US Patent 6370673
    • D. Hill, "Method and System for High Speed Detailed Placement of Cells Within an Integrated Circuit Design," US Patent 6370673, 2001.
    • (2001)
    • Hill, D.1
  • 23
    • 16244391451 scopus 로고    scopus 로고
    • An analytic placer for mixed-size placement and timing-driven placement
    • _, "An Analytic Placer for Mixed-Size Placement and Timing-Driven Placement," in Proc. IEEE International Conference on Computer Aided Design, 2004, pp. 565-572.
    • (2004) Proc. IEEE International Conference on Computer Aided Design , pp. 565-572
  • 29
    • 18744376720 scopus 로고    scopus 로고
    • Non-linear optimization system and method for wire length and delay optimization for an automatic electric circuit placer
    • US Patent 6301693
    • W. Naylor, "Non-Linear Optimization System and Method for Wire Length and Delay Optimization for an Automatic Electric Circuit Placer," US Patent 6301693, 2001.
    • (2001)
    • Naylor, W.1
  • 35
    • 2942639682 scopus 로고    scopus 로고
    • FastPlace: Efficient analytical placement using cell shifting, iterative local refinement and a hybrid net model
    • N. Viswanathan and C. Chu, "FastPlace: Efficient Analytical Placement Using Cell Shifting, Iterative Local Refinement and a Hybrid Net Model," in Proc. ACM/IEEE International Symposium on Physical Design, 2004, pp. 26-33.
    • (2004) Proc. ACM/IEEE International Symposium on Physical Design , pp. 26-33
    • Viswanathan, N.1    Chu, C.2
  • 36
    • 29144530525 scopus 로고    scopus 로고
    • FastPlace: An analytical placer for mixed-mode designs
    • _, "FastPlace: An Analytical Placer for Mixed-Mode Designs," in Proc. ACM/IEEE International Symposium on Physical Design, 2005, pp. 221-223.
    • (2005) Proc. ACM/IEEE International Symposium on Physical Design , pp. 221-223
  • 38
    • 2942686108 scopus 로고    scopus 로고
    • Algorithms for detailed placement of standard cells
    • _, "Algorithms for detailed Placement of Standard Cells," in Design, Automation and Test in Europe, 1998, pp. 321-324.
    • (1998) Design, Automation and Test in Europe , pp. 321-324


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.