SCOPUS 정보 검색 플랫폼

Proceedings of the International Symposium on Physical Design

Volumn , Issue , 2011, Pages 115-121

INTEGRA: Fast multi-bit flip-flop clustering for clock power saving based on interval graphs

(5) Jiang, Iris Hui Ru a Chang, Chih Long a Yang, Yu Ming a Tsai, Evan Y W b Chen, Lancer S F b

a NATIONAL CHIAO TUNG UNIVERSITY (Taiwan)

b FARADAY TECHNOLOGY CORPORATION (Taiwan)

Author keywords

clock power; coordinate transformation; interval graph; multi bit flip flops; post placement optimization

Indexed keywords

CLOCK NETWORK; CLOCK SIGNAL; CLUSTERING SCHEME; COORDINATE TRANSFORMATION; DYNAMIC POWER; FAST OPERATION; IC DESIGNS; INTERVAL GRAPH; MANHATTAN DISTANCE; MULTI-BITS; PARTIAL SEQUENCES; POST-PLACEMENT OPTIMIZATION; POWER SAVINGS; PROBLEM INSTANCES; SINGLE-BIT; SKEW CONTROL;

ALGORITHMS; DESIGN; DYNAMICS; ELECTRIC CLOCKS; LINEAR TRANSFORMATIONS; OPTIMIZATION; POWER SUPPLY CIRCUITS;

FLIP FLOP CIRCUITS;

EID: 79955055429 PISSN: None EISSN: None Source Type: Conference Proceeding
DOI: 10.1145/1960397.1960424 Document Type: Conference Paper

Times cited : (22)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.