Memristors: Devices, models, and applications [scanning the issue]

Proceedings of the IEEE

Volumn 100, Issue 6, 2012, Pages 1911-1919

  Mazumder, Pinaki ^a   Kang, Sung Mo ^b   Waser, Rainer ^c  

^a UNIVERSITY OF MICHIGAN   (United States)

^b University of California Santa Cruz   (United States)

^c RWTH AACHEN UNIVERSITY   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

CRYPTOGRAPHY; GERMANIUM COMPOUNDS; MANGANITES; PIECEWISE LINEAR TECHNIQUES; SELENIUM COMPOUNDS; SILVER COMPOUNDS; YTTRIUM COMPOUNDS;

ANALOG COMPONENTS; DEVICE ENGINEERING; DEVICE VARIATIONS; DIGITAL LOGIC APPLICATIONS; EXPERIMENTAL DEMONSTRATIONS; IMAGE ENCRYPTIONS; NEUROMORPHIC SYSTEMS; RESISTIVE SWITCHING;

MEMRISTORS;

EID: 84861125640     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2012.2190812     Document Type: Conference Paper

References (92)

1. G. S. Snider, "Spike-timing-dependent learning in memristive nanodevices, "in Proc. IEEE Int. Symp. Nanoscale Architectures, 2008, pp. 85-92.
2. Y. V. Pershin and M. Di Ventra, "Experimental demonstration of associative memory with memristive neural networks, "Neural Netw., vol. 23, no. 7, pp. 881-886, 2010.
3. W. Yi, F. Perner, M. S. Qureshi, H. Abdalla, M. D. Pickett, J. J. Yang, M.-X. Zhang, G. Medeiros-Ribeiro, and R. S. Williams, "Feedback write scheme for memristive switching devices, "Appl. Phys. A, Mater. Sci. Process., vol. 102, no. 4, pp. 973-982, 2011.
4. G. W. Burr, B. N. Kurdi, J. C. Scott, C. H. Lam, K. Gopalakrishnan, and R. S. Shenoy, "Overview of candidate device technologies for storage-class memory, "IBM J. Res. Develop., vol. 52, no. 4.5, pp. 449-464, 2008.
5. R. Annunziata, P. Zuliani, M. Borghi, G. De Sandre, L. Scotti, C. Prelini, M. Tosi, I. Tortorelli, and F. Pellizzer, "Phase change memory technology for embedded non volatile memory applications for 90 nm and beyond, "in Proc. IEEE Int. Electron Devices Meeting, "altimore, MD, 2009, DOI: 10.1109/IEDM.2009.5424413.
6. G. Servalli, "A 45 nm generation phase change memory technology, "in Proc. IEEE Int. Electron Devices Meeting, "altimore, MD, 2009, DOI: 10.1109/IEDM.2009.5424409.
7. H. P. Wong, S. Raoux, S. Kim, J. Liang, J. P. Reifenberg, B. Rajendran, M. Asheghi, and K. E. Goodson, "Phase change memory, "Proc. IEEE, vol. 98, no. 12, pp. 2201-2227, Dec. 2010.
8. S. Raoux, G. W. Burr, M. J. Breitwisch, C. T. Rettner, Y. C. Chen, R. M. Shelby, M. Salinga, D. Krebs, S.-H. Chen, H.-L. Lung, and C. H. Lam, "Phase-change random access memory: A scalable technology, "IBM J. Res. Develop., vol. 52, no. 4.5, pp. 465-479, 2008.
9. T. W. Hickmott, "Low-frequency negative resistance in thin anodic oxide films, "J. Appl. Phys., vol. 33, pp. 2669-2682, 1962.
10. J. F. Gibbons and W. E. Beadle, "Switching properties of thin NiO films, "Solid-State Electron., vol. 7, pp. 785-790, 1964.
11. J. G. Simmons and R. R. Verderber, "New thin-film resistive memory, "Radio Electron. Eng., vol. 34, pp. 81-89, 1967.
12. Y. Hirose and H. Hirose, "Polarity-dependent memory switching and behaviour of Ag dendrite in Ag-photodoped amorphous As2S3 films, "J. Appl. Phys., vol. 47, pp. 2767-2772, 1976.
13. G. Dearnaley, A. M. Stoneham, and D. V. Morgan, "Electrical phenomena in amorphous oxide films, "Rep. Progr. Phys., vol. 33, pp. 1129-1191, 1970.
14. D. P. Oxley, "Electroforming, switching and memory effects in oxide thin films, "Electrocompon. Sci. Technol., vol. 3, pp. 217-224, 1977.
15. H. Pagnia and N. Sotnik, "Bistable switching in electroformed metal-insulator-metal devices, "Phys. Stat. Sol., vol. 108, pp. 11-65, 1988. (Pubitemid 18664267)
16. A. Asamitsu, Y. Tomioka, H. Kuwahara, and Y. Tokura, "Current switching of resistive states in magnetoresistive manganites, "Nature, vol. 388, pp. 50-52, 1997. (Pubitemid 27283883)
17. M. N. Kozicki, M. Yun, L. Hilt, and A. Singh, "Applications of programmable resistance changes in metal-doped chalcogenides, "J. Electrochem. Soc., vol. 1-12, pp. 298-309, 1999.
18. A. Beck, J. G. Bednorz, C. Gerber, C. Rossel, and D. Widmer, "Reproducible switching effect in thin oxide films for memory applications, "Appl. Phys. Lett., vol. 77, pp. 139-141, 2000.
19. K. Szot, W. Speier, G. Bihlmayer, and R. Waser, "Switching the electrical resistance of individual dislocations in single-crystalline SrTiO3, "Nature Mater., vol. 5, pp. 312-320, 2006.
20. R. Waser, R. Dittmann, G. Staikov, and K. Szot, "Redox-based resistive switching memories-nanoionic mechanisms, prospects, challenges, "Adv. Mater., vol. 21, pp. 2632-2663, 2009.
21. D. B. Strukov, G. S. Snider, D. R. Stewart, and R. S. Williams, "The missing memristor found, "Nature, vol. 453, pp. 80-83, 2008. (Pubitemid 351630336)
22. J. J. Yang, M. D. Pickett, X. Li, D. A. A. Ohlberg, D. R. Stewart, and R. S. Williams, "Memristive switching mechanism for metal/oxide/metal nanodevices, "Nature Nanotechnol., vol. 3, pp. 429-433, 2008.
23. R. Waser and M. Aono, "Nanoionics-based resistive switching memories, "Nature Mater., vol. 6, pp. 833-840, 2007. (Pubitemid 350064191)
24. I. G. Baek, M. S. Lee, S. Seo, M. J. Lee, D. H. Seo, D.-S. Suh, J. C. Park, S. 0. Park, H. S. Kim, I. K. Yoo, U.-I. Chung, and I. T. Moon, "Highly scalable non-volatile resistive memory using simple binary oxide driven by asymmetric unipolar voltage pulses, "in Tech. Dig. IEEE Int. Electron Device Meeting, 2004, pp. 587-590. (Pubitemid 40928360)
25. D. Ielmini, R. Bruchhaus, and R. Waser, "Thermochemical resistive switching: Materials, mechanisms, scaling projections, "Phase Transit., vol. 84, pp. 570-602, 2011.
26. D. S. Jeong, H. Schroeder, and R. Waser, "Coexistence of bipolar and unipolar resistive switching behaviors in a Pt/TiO2/Pt stack, "Electrochem. Solid State Lett., vol. 10, pp. G51-G53, 2007. (Pubitemid 46920043)
27. R. Meyer, L. Schloss, J. Brewer, R. Lambertson, W. Kinney, J. Sanchez, and D. Rinerson, "Oxide dual-layer memory element for scalable non-volatile cross-point memory technology, "in Proc. Nonvolatile Memory Technol. Symp., 2008, pp. 54-58.
28. M. D. Pickett, D. B. Strukov, J. L. Borghetti, J. J. Yang, G. S. Snider, D. R. Stewart, and R. S. Williams, "Switching dynamics in titanium dioxide memristive devices, "J. Appl. Phys., vol. 106, pp. 074508-1-074508-6, 2009.
29. S. Menzel, M. Waters, A. Marchewka, U. Böttger, R. Dittmann, and R. Waser, "Origin of the ultra-nonlinear switching kinetics in oxide-based resistive switches, "Adv. Funct. Mater., vol. 21, pp. 4487-4492, 2011.
30. K. Terabe, T. Hasegawa, T. Nakayama, and M. Aono, "Quantized conductance atomic switch, "Nature, vol. 433, pp. 47-50, 2005. (Pubitemid 40101138)
31. S. Dietrich, M. Angerbauer, M. Ivanov, D. Gogl, H. Hoenigschmid, M. Kund, C. Liaw, M. Markert, R. Symanczyk, L. Altimime, S. Bournat, and G. Mueller, "A nonvolatile 2-Mbit CBRAM memory core featuring advanced read and program control, "IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 839-845, Apr. 2007. (Pubitemid 46495401)
32. I. Valov, R. Waser, J. R. Jameson, and M. N. Kozicki, "Electrochemical metallization memories-fundamentals, applications, prospects, "Nanotechnology, vol. 22, pp. 254003/1-254003/22, 2011.
33. B. J. Choi, D. S. Jeong, S. K. Kim, C. Rohde, S. Choi, J. H. Oh, H. J. Kim, C. S. Hwang, K. Szot, R. Waser, B. Reichenberg, and S. Tiedke, "Resistive switching mechanism of TiO2 thin films grown by atomic-layer deposition, "J. Appl. Phys., vol. 98, pp. 3715-1-3715-10, 2005.
34. A. Sawa, "Resistive switching in transition metal oxides, "Mater. Today, vol. 11, pp. 28-36, 2008. (Pubitemid 351680723)
35. H. Sim, D. Choi, D. Lee, S. Seo, M.-J. Lee, I.-K. Yoo, and H. Hwang, "Resistance-switching characteristics of polycrystalline Nb2O5 for nonvolatile memory application, "IEEE Electron Device Lett., vol. 26, no. 5, pp. 292-294, May 2005. (Pubitemid 40708833)
36. R. Muenstermann, T. Menke, R. Dittmann, and R. Waser, "Coexistence of filamentary and homogeneous resistive switching in Fe-doped SrTiO3 thin-film memristive devices, "Adv. Mater., vol. 22, pp. 4819-4822, 2010.
37. Y. V. Pershin and M. Di Ventra, "Memory effects in complex materials and nanoscale systems, "Adv. Phys., vol. 60, pp. 145-227, 2011.
38. Y. Ho, G. M. Huang, and P. Li, "Nonvolatile memristor memory: Sevice characteristics and design implications, "in Proc. Int. Cong. Comput.-Aided Design, 2009, pp. 485-490.
39. M.-J. Lee, Y. Park, S. Kang, S.-E. Ahn, C. Lee, K. Kim, W. Xianyu, G. Stefanovich, J.-H. Lee, S.-J. Chung, Y.-H. Kim, C.-S. Lee, J.-B. Park, and I.-K. Yoo, "2-stack 1D-1R cross-point structure with oxide diodes as switch elements for high density resistance RAM applications, "in Proc. IEEE Int. Electron Devices Meeting, 2007, pp. 771-774.
40. E. Linn, R. Rosezin, C. Kuegeler, and R. Waser, "Complementary resistive switches for passive nanocrossbar memories, "Nature Mater., vol. 9, pp. 403-406, 2010.
41. I. E. Ebong and P. Mazumder, "Self-controlled writing and erasing in a Memristor crossbar memory, "IEEE Trans. Nanotechnol., vol. 10, no. 6, pp. 1454-1463, Nov. 2011.
42. O. V. Pascal, R. Warren, J. K. Philip, R. S. Duncan, S. Joseph, and R. S. Williams, "Writing to and reading from a nano-scale crossbar memory based on memristors, "Nanotechnology, vol. 20, no. 42, 425204, 2009.
43. M. Harika, S. R. Garrett, H. Xiaoli, and W. Wei, "Design considerations for variation tolerant multilevel CMOS/nano memristor memory, "in Proc. Great Lakes Symp. Very Large Scale Integr. (VLSI), 2010, pp. 287-292.
44. H. Akinaga and H. Shima, "Resistive random access memory (ReRAM) based on metal oxides, "Proc. IEEE, vol. 98, no. 12, pp. 2237-2251, Dec. 2010.
45. K. Eshraghian, K.-R. Cho, O. Kavehei, S.-K. Kang, D. Abbott, and S.-M. S. Kang, "Memristor MOS content addressable memory (MCAM): Hybrid architecture for future high performance search engines, "IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 19, no. 8, pp. 1407-1417, Aug. 2011.
46. W. Robinett, M. Pickett, J. Borghetti, Q. Xia, G. S. Snider, G. Medeiros-Ribeiro, and R. S. Williams, "A memristor-based nonvolatile latch circuit, "Nanotechnology, vol. 21, no. 23, 235203, 2010.
47. T. Raja and S. Mourad, "Digital logic implementation in memristor-based crossbarsVA tutorial, "in Proc. 5th IEEE Int. Symp. Electron. Design Test Appl., 2010, pp. 303-309.
48. J. Borghetti, Z. Li, J. Straznicky, X. Li, D. A. A. Ohlberg, W. Wu, D. R. Stewart, and R. S. Williams, "A hybrid nanomemristor/transistor logic circuit capable of self-programming, "Proc. Nat. Acad. Sci., vol. 106, no. 6, pp. 1699-1703, Feb. 10, 2009.
49. W. Wei, T. T. Jing, and B. Butcher, "FPGA based on integration of memristors and CMOS devices, "in Proc. IEEE Int. Symp. Circuits Syst., 2010, pp. 1963-1966.
50. W. Wei, T. T. Jing, and B. Butcher, "FPGA based on integration of memristors and CMOS devices, "in Proc. IEEE Int. Symp. Circuits Syst., 2010, pp. 1963-1966.
51. J. Cong and X. Bingjun, "mrFPGA: A novel FPGA architecture with memristor-based reconfiguration, "in Proc. IEEE/ACM Int. Symp. Nanoscale Architectures, 2011, DOI: 10.1109/NANOARCH.2011.5941476.
52. Q. Xia, W. Robinett, M. W. Cumbie, N. Banerjee, T. J. Cardinali, J. J. Yang, W. Wu, X. Li, W. M. Tong, D. B. Strukov, G. S. Snider, G. Medeiros-Ribeiro, and R. S. Williams, "Memristor-CMOS hybrid integrated circuits for reconfigurable logic, "Nano Lett., vol. 9, no. 10, pp. 3640-3645, 2009.
53. D. Mian and Z. Lin, "Nanowire crossbar logic and standard cell-based integration, "IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 8, pp. 997-1007, Aug. 2009.
54. L. Eero and L. Mika, "Stateful implication logic with memristors, "in Proc. IEEE/ACM Int. Symp. Nanoscale Architectures, 2009, pp. 33-36.
55. K. Kim, S. Shin, and S.-M. Kang, "Field programmable stateful logic array, "IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 30, no. 12, pp. 1800-1813, Dec. 2011.
56. K. Bickerstaff and E. E. Swartzlander, "Memristor-based arithmetic, "in Proc. Conf. 44th Asilomar Conf. Signals Syst. Comput., 2010, pp. 1173-1177.
57. J. Rajendran, H. Manem, R. Karri, and G. S. Rose, "Memristor based programmable threshold logic array, "in Proc. IEEE/ACM Int. Symp. Nanoscale Architectures, 2010, pp. 5-10.
58. Y. V. Pershin and M. Di Ventra, "Practical approach to programmable analog circuits with memristors, "IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 8, pp. 1857-1864, Aug. 2010.
59. S. Shin, K. Kim, and S. M. Kang, "Memristor applications for programmable analog ICs, "IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 266-274, Mar. 2010.
60. M. Itoh and L. O. Chua, "Memristor cellular automata and memristor discrete-time cellular neural networks, "Int. J. Bifurcat. Chaos, vol. 19, no. 11, pp. 3605-3656, 2009.
61. E. Lehtonen and M. Laiho, "CNN using memristors for neighborhood connections, "in Proc. 12th Int. Workshop Cellular Nanoscale Netw. Appl., 2010, DOI: 10.1109/CNNA. 2010.5430304.
62. A. Wu, Z. Zeng, X. Zhu, and J. Zhang, "Exponential synchronization of memristor-based recurrent neural networks with time delays, "Neurocomputing, vol. 74, no. 17, pp. 3043-3050, 2011.
63. K. Witrisal, "Memristor-based stored-reference receiver-the UWB solution?[ Electron. Lett.vol. 45, no. 14, pp. 713-714, 2009.
64. F. Merrikh-Bayat and S. Bagheri-Shouraki, "Mixed analog-digital crossbar-based hardware implementation of sign-sign LMS adaptive filter, "Analog Integr. Circuits Signal Process., vol. 66, no. 1, pp. 41-48, 2011.
65. A. Talukdar, A. G. Radwan, and K. N. Salama, "Generalized model for Memristor-based Wien family oscillators, "Microelectron. J., vol. 42, no. 9, pp. 1032-1038, 2011.
66. T. Driscoll, Y. Pershin, D. Basov, and M. Di Ventra, "Chaotic memristor, "Appl. Phys. A, Mater. Sci. Process., vol. 102, no. 4, pp. 885-889, 2011.
67. M. Itoh, "Memristor oscillators, "Int. J. Bifurcat. Chaos Appl. Sci. Eng., vol. 18, no. 11, pp. 3183-3206, 2008.
68. B. Muthuswamy and P. Kokate, "Memristor-based chaotic circuits, "IETE Tech. Rev., vol. 26, no. 6, pp. 417-429, 2009.
69. B. C. Bao, Z. Liu, and J. P. Xu, "Steady periodic memristor oscillator with transient chaotic behaviours, "Electron. Lett., vol. 46, no. 3, pp. 237-238, 2010.
70. B. Muthuswamy, "Implementing memristor based chaotic circuits, "Int. J. Bifurcat. Chaos Appl. Sci. Eng., vol. 20, no. 5, pp. 1335-1350, 2010.
71. Z.-H. Lin and H.-X. Wang, "Image encryption based on chaos with PWL memristor in Chua's circuit, "in Proc. Int. Conf. Commun. Circuits Syst., 2009, pp. 964-968.
72. A. Afifi, A. Ayatollahi, and F. Raissi, "Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits, "in Proc. Eur. Conf. Circuit Theory Design, 2009, pp. 563-566.
73. I. Ebong and P. Mazumder, "Memristor based STDP learning network for position detection, "in Proc. Int. Conf. Microelectron., 2010, pp. 292-295.
74. S. H. Jo, T. Chang, I. Ebong, B. B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale memristor device as synapse in neuromorphic systems, "Nano Lett., vol. 10, no. 4, pp. 1297-1301, 2010.
75. G. S. Snider, "Self-organized computation with unreliable, memristive nanodevices, "Nanotechnology, vol. 18, no. 36, pp. 365202-365215, 2007.
76. Kyungah, K. Insung, S. Jung,M. Jo, S. Park, J. Park, J. Shin, K. P. Biju, J. Kong, K. Lee, B. Lee, and H. Hwang, "Analog memory and spike-timing-dependent plasticity characteristics of a nanoscale titanium oxide bilayer resistive switching device, "Nanotechnology, vol. 22, no. 25, 254023, 2011.
77. K. Likharev, A. Mayr, I. Muckra, and Ö. TÜRel, "CrossNets: High-performance neuromorphic architectures for CMOL circuits, "Ann. New York Acad. Sci., vol. 1006, no. 1, pp. 146-163, 2003. (Pubitemid 38064782)
78. J. A. Pérez-Carrasco, C. Zamarreno-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, "On neuromorphic spiking architectures for asynchronous STDP memristive systems, "in Proc. IEEE Int. Symp. Circuits Syst., 2010, pp. 1659-1662.
79. S.-J. Choi, G.-B. Kim, K. Lee, K.-H. Kim, W.-Y. Yang, S. Cho, H.-J. Bae, D.-S. Seo, S.-I. Kim, and K.-J. Lee, "Synaptic behaviors of a single metal-oxide-metal resistive device, "Appl. Phys. A, Mater. Sci. Process., vol. 102, no. 4, pp. 1019-1025, 2011.
80. G. D. Howard, E. Gale, L. Bull, B. D. L. Costello, and A. Adamatzky, "Evolving spiking networks with variable memristors, "in Proc. 13th Annu. Conf. Genetic Evol. Comput., Dublin, Ireland, 2011, pp. 1275-1282.
81. D. Querlioz, O. Bichler, and C. Gamrat, "Simulation of a memristor-based spiking neural network immune to device variations, "in Proc. Int. Joint Conf. Neural Netw., 2011, pp. 1775-1781.
82. F. Merrikh-Bayat, S. B. Shouraki, and A. Rohani, "Memristor crossbar-based hardware implementation of the IDS method, "IEEE Trans. Fuzzy Syst., vol. 19, no. 6, pp. 1083-1096, Dec. 2011.
83. S. D. Ha and S. Ramanathan, "Adaptive oxide electronics: A review, "J. Appl. Phys., vol. 110, no. 7, pp. 071101-071101-20, Oct. 2011.
84. L. O. Chua, "MemristorVThe missing circuit element, "IEEE Trans. Circuit Theory, vol. CT-18, no. 5, pp. 505-517, Sep. 1971.
85. L. O. Chua and S. M. Kang, "Memristive devices and systems, "Proc. IEEE, vol. 64, no. 2, pp. 209-223, Feb. 1976.
86. C. M. Jung, E. S. Lee, K. S. Min, and S. M. Kang, "Compact verilogVA model of phase-change RAM transient behaviors for multi-level applications, "Semicond. Sci. Technol., vol. 10, 105018, Sep. 2011.
87. S. Shin, K. Kim, and S.-M. Kang, "Compact models for memristors based on charge-flux constitutive relationships, "IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 4, pp. 590-598, Apr. 2010.
88. Z. Biolek, D. Biolek, and V. Biolkova, "SPICE model of memristor with nonlinear dopant drift, "Radioengineering, vol. 18, no. 1, pp. 210-214, 2009.
89. D. Biolek, Z. Biolek, and V. Biolkova, "SPICE modeling of memristive, memcapacitative and meminductive systems, "in Proc. Eur. Conf. Circuit Theory Design, Aug. 2009, pp. 249-252.
90. A. Rak and G. Cserey, "Macromodeling of the memristor in SPICE, "IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 29, no. 4, pp. 632-636, Apr. 2010.
91. D. Batas and H. Fiedler, "A memristor SPICE implementation and a new approach for magnetic flux-controlled memristor modeling, "IEEE Trans. Nanotechnol., vol. 10, no. 2, pp. 250-255, Mar. 2011.
92. H. Abdalla and M. D. Pickett, "Spice modeling of memristors, "in Proc. Int. Symp. Circuits Syst., 2011, pp. 1832-1835.