Simulation of a memristor-based spiking neural network immune to device variations

Proceedings of the International Joint Conference on Neural Networks

Volumn , Issue , 2011, Pages 1775-1781

  Querlioz, Damien ^a   Bichler, Olivier ^b   Gamrat, Christian ^b  

^a UNIVERSITÉ PARIS SACLAY   (France)

^b DIF   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CODING SCHEME; DESIGN METHODOLOGY; DEVICE VARIATIONS; NANO-DEVICES; SPIKE TIMING DEPENDENT PLASTICITIES; SPIKING NEURAL NETWORKS; SUPERVISED NETWORK; SYSTEM LEVEL SIMULATION;

COMPUTER SIMULATION; MEMRISTORS; NETWORK PERFORMANCE; PASSIVE FILTERS; PHYSIOLOGY; RESISTORS;

NEURAL NETWORKS;

EID: 80054729052     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IJCNN.2011.6033439     Document Type: Conference Paper

References (35)

1. D.B. Strukov, G.S. Snider, D.R. Stewart, and R.S. Williams, "The missing memristor found," Nature, vol. 453, May. 2008, pp. 80-83.
2. E. Marder and J.-M. Goaillard, "Variability, compensation and homeostasis in neuron and network function," Nat. Rev. Neurosci., vol. 7, Jul. 2006, pp. 563-574.
3. G. Snider, "Instar and outstar learning with memristive nanodevices," Nanotechnol., vol. 22, 2011, p. 015201.
4. S.H. Jo, T. Chang, I. Ebong, B.B. Bhadviya, P. Mazumder, and W. Lu, "Nanoscale Memristor Device as Synapse in Neuromorphic Systems," Nano Lett., vol. 10, Apr. 2010, pp. 1297-1301.
5. G.S. Snider, "Self-organized computation with unreliable, memristive nanodevices," Nanotechnol., vol. 18, 2007, p. 365202.
6. M. Versace and B. Chandler, "The brain of a new machine," IEEE Spectrum, vol. 47, 2010, pp. 30-37.
7. J.H. Lee and K.K. Likharev, "Defect-tolerant nanoelectronic pattern classifiers," Int. J. Circuit Theory Appl., vol. 35, 2007, pp. 239-264.
8. G.S. Snider, "Spike-timing-dependent learning in memristive nanodevices," Prof. of IEEE International Symposium on Nanoscale Architectures 2008 (NANOARCH), 2008, pp. 85-92.
9. J.A. Pérez-Carrasco, C. Zamarreño-Ramos, T. Serrano-Gotarredona, and B. Linares-Barranco, "On neuromorphic spiking architectures for asynchronous STDP memristive systems," Proc. of 2010 IEEE Int. Symp. Circuits Systems (ISCAS), 2010, pp. 1659-1662.
10. G. Snider, R. Amerson, D. Carter, H. Abdalla, M.S. Qureshi, J. Léveillé, M. Versace, H. Ames, S. Patrick, B. Chandler, A. Gorchetchnikov, and E. Mingolla, "From Synapses to Circuitry: Using Memristive Memory to Explore the Electronic Brain," Computer, vol. 44, 2011, pp. 21-28.
11. Y. Lecun, L. Bottou, Y. Bengio, and P. Haffner, "Gradient-based learning applied to document recognition," Proc. IEEE, vol. 86, 1998, pp. 2278-2324.
12. G.W. Burr, B.N. Kurdi, J.C. Scott, C.H. Lam, K. Gopalakrishnan, and R.S. Shenoy, "Overview of candidate device technologies for storage-class memory," IBM J. Res. Dev., 2008.
13. F. Alibart, S. Pleutin, D. Guérin, C. Novembre, S. Lenfant, K. Lmimouni, C. Gamrat, and D. Vuillaume, "An Organic Nanoparticle Transistor Behaving as a Biological Spiking Synapse," Adv. Funct. Mater., vol. 20, 2010, pp. 330-337.
14. G. Agnus, W. Zhao, V. Derycke, A. Filoramo, Y. Lhuillier, S. Lenfant, D. Vuillaume, C. Gamrat, and J.-P. Bourgoin, "Two-Terminal Carbon Nanotube Programmable Devices for Adaptive Architectures," Adv. Mater., vol. 22, 2010, pp. 702-706.
15. A. Afifi, A. Ayatollahi, and F. Raissi, "Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits," European Conf. on Circuit Theory and Design (ECCTD), 2009, pp. 563-566.
16. H. Markram, J. Lubke, M. Frotscher, and B. Sakmann, "Regulation of Synaptic Efficacy by Coincidence of Postsynaptic APs and EPSPs," Science, vol. 275, Jan. 1997, pp. 213-215.
17. G.-Q. Bi and M.-M. Poo, "Synaptic modification by correlated activity: Hebb's Postulate Revisited," Annu. Rev. Neurosci., vol. 24, 2001, pp. 139-166.
18. Y. Dan and M.-ming Poo, "Spike Timing-Dependent Plasticity of Neural Circuits," Neuron, vol. 44, 2004, pp. 23-30.
19. A. Gorchetchnikov, M. Versace, and M. Hasselmo, "A model of STDP based on spatially and temporally local information: Derivation and combination with gated decay," Neural Networks, vol. 18, Jul. 2005, pp. 458-466.
20. S.H. Jo and W. Lu, "CMOS Compatible Nanoscale Nonvolatile Resistance Switching Memory," Nano Lett., vol. 8, pp. 392-397.
21. J. Borghetti, G.S. Snider, P.J. Kuekes, J.J. Yang, D.R. Stewart, and R.S. Williams, "'Memristive' switches enable 'stateful' logic operations via material implication," Nature, vol. 464, Apr. 2010, pp. 873-876.
22. J.R. Heath, P.J. Kuekes, G.S. Snider, and R.S. Williams, "A defecttolerant computer architecture: Opportunities for nanotechnology," Science, vol. 280, 1998, p. 1716-1721.
23. A. DeHon, "Array-based architecture for FET-based, nanoscale electronics," IEEE Trans. Nanotechnol., vol. 2, 2003, pp. 23-32.
24. R. Guyonneau, R. VanRullen, and S.J. Thorpe, "Neurons Tune to the Earliest Spikes Through STDP," Neural Computation, vol. 17, Apr. 2005, pp. 859-879.
25. T. Masquelier and S.J. Thorpe, "Unsupervised Learning of Visual Features through Spike Timing Dependent Plasticity," PLoS Comput Biol, vol. 3, Feb. 2007, p. e31.
26. J.M. Brader, W. Senn, and S. Fusi, "Learning Real-World Stimuli in a Neural Network with Spike-Driven Synaptic Dynamics," Neural Computation, vol. 19, Nov. 2007, pp. 2881-2912.
27. B. Nessler, M. Pfeiffer, and W. Maass, "STDP enables spiking neurons to detect hidden causes of their inputs," Advances in Neural Information Processing Systems (NIPS'09), p. 1357-1365.
28. J.V. Arthur and K. Boahen, "Learning in silicon: Timing is everything," Advances in neural information processing systems, vol. 18, 2006, p. 281-1185.
29. P. Livi and G. Indiveri, "A current-mode conductance-based silicon neuron for address-event neuromorphic systems," Proc. of 2009 IEEE International Symposium on Circuits and Systems (ISCAS), 2009, pp. 2898-2901.
30. P. Lichtsteiner, C. Posch, and T. Delbruck, "A 128× 128 120 dB 15 μs Latency Asycnhronous Temporal Contrast Vision Sensor," IEEE Journal of Solid-State Circuits, vol. 43, 2008, pp. 566-576.
31. V. Chan, S.-C. Liu, and A. van Schaik, "AER EAR: A Matched Silicon Cochlea Pair With Address Event Representation Interface," IEEE Trans. Circuits Syst. Regul. Pap., vol. 54, 2007, pp. 48-59.
32. M.D. Pickett, D.B. Strukov, J.L. Borghetti, J.J. Yang, G.S. Snider, D.R. Stewart, and R.S. Williams, "Switching dynamics in titanium dioxide memristive devices," J. Appl. Phys., vol. 106, 2009, p. 074508.
33. G. Indiveri, E. Chicca, and R. Douglas, "A VLSI array of lowpower spiking neurons and bistable synapses with spike-timing dependent plasticity," IEEE Transactions on Neural Networks, vol. 17, 2006, pp. 211-221.
34. C. Bartolozzi, O. Nikolayeva, and G. Indiveri, "Implementing homeostatic plasticity in VLSI networks of spiking neurons," 15th IEEE International Conference on Electronics, Circuits and Systems (ICECS 2008), 2008, pp. 682-685.
35. D.C. Ciresan, U. Meier, L.M. Gambardella, and J. Schmidhuber, "Deep Big Simple Neural Nets Excel on Handwritten Digit Recognition," CoRR abs/1003.0358, Mar. 2010.