FPGA based on integration of memristors and CMOS devices

ISCAS 2010 - 2010 IEEE International Symposium on Circuits and Systems: Nano-Bio Circuit Fabrics and Systems

Volumn , Issue , 2010, Pages 1963-1966

  Wang, Wei ^a   Jing, Tom T ^a   Butcher, Brian ^a  

^a STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA REDUCTION; BLOCK MEMORIES; CMOS COMPATIBLE; CMOS DEVICES; DENSITY ENHANCEMENT; FPGA ARCHITECTURES; LOWER-POWER CONSUMPTION; MEMRISTOR; POWER REDUCTIONS; RECONFIGURABLE ARCHITECTURE; ROUTING SWITCHES; SIMULATION RESULT;

FABRICS;

ARCHITECTURE;

EID: 77956002550     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2010.5537010     Document Type: Conference Paper

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