Spike-timing-dependent learning in memristive nanodevices

2008 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2008

Volumn , Issue , 2008, Pages 85-92

  Snider, Greg S ^a  

^a HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

Adaptive systems; Analog memories; Learning systems; Neural network hardware; Nonlinear circuits

Indexed keywords

DIFFERENCE EQUATIONS; EDUCATION; FAULT TOLERANCE; LAWS AND LEGISLATION; LEARNING SYSTEMS; MACHINE DESIGN; METALS; NANOSTRUCTURED MATERIALS; NANOTECHNOLOGY; NEURONS; QUALITY ASSURANCE; RELIABILITY; TELECOMMUNICATION; TIME MEASUREMENT; TIMING CIRCUITS;

ADAPTIVE SYSTEMS; ANALOG MEMORIES; INTERNATIONAL SYMPOSIUM; LEARNING DYNAMICS; LEARNING LAWS; MASSIVE PARALLELISM; METAL OXIDES; MODULATED SIGNALS; NANO SCALING; NANO-DEVICES; NANO-SCALE ARCHITECTURE; NEURAL NETWORK HARDWARE; NEUROMORPHIC; NONLINEAR CIRCUITS; ORDERS-OF-MAGNITUDE; POST-SYNAPTIC NEURONS; POWER DISSIPATIONS; PULSE WIDTHS; SINGLE CHIPS; SPIKE-TIMING; SPIKE-TIMING DEPENDENT PLASTICITY; STATE VARIABLES; TIME-DIVISION MULTIPLEXING;

LEARNING ALGORITHMS;

EID: 51949112980     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2008.4585796     Document Type: Conference Paper

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