Design considerations for variation tolerant multilevel CMOS/Nano memristor memory

Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI

Volumn , Issue , 2010, Pages 287-292

  Manem, Harika ^a   Rose, Garrett S ^a   He, Xiaoli ^b   Wang, Wei ^b  

^a POLYTECHNIC UNIVERSITY   (United States)

^b STATE UNIVERSITY OF NEW YORK   (United States)

Author keywords

CMOS nano; memristor; multi level memories

Indexed keywords

DESIGN CONSIDERATIONS; DESIGN CONSTRAINTS; LOW-POWER CONSUMPTION; MEMORY ARCHITECTURE; MEMORY SYSTEMS; MEMRISTOR; MOLECULAR SCALE; MULTILEVEL MEMORY; NANO SCALE; NOISE MARGINS; TECHNOLOGY MIGRATION;

LAKES;

DESIGN;

EID: 77954466597     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1785481.1785548     Document Type: Conference Paper

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