Memristor based programmable threshold logic array

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, NANOARCH 2010

Volumn , Issue , 2010, Pages 5-10

  Rajendran, Jeyavijayan ^a   Manem, Harika ^a   Karri, Ramesh ^a   Rose, Garrett S ^a  

^a POLYTECHNIC UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AREA EFFICIENT; ARRAY ARCHITECTURE; AVERAGE POWER; DELAY PENALTY; EMERGING COMPUTING TECHNOLOGIES; LOOK-UP-TABLE; MEMRISTOR; PROPOSED ARCHITECTURES; THRESHOLD GATES; TRANSISTOR COUNT;

ARCHITECTURE; NANOSTRUCTURED MATERIALS; RESONANT TUNNELING; THRESHOLD LOGIC;

BOOLEAN FUNCTIONS;

EID: 77955720869     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NANOARCH.2010.5510933     Document Type: Conference Paper

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