Optimum wire sizing of RLC interconnect with repeaters

Integration, the VLSI Journal

Volumn 38, Issue 2, 2004, Pages 205-225

  El Moursy, Magdy A ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

On chip inductance; Power delay product; Propagation delay; Repeater insertion; Transient power dissipation; Wire sizing

Indexed keywords

ALGORITHMS; CAPACITANCE; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; LIGHT PROPAGATION; OPTIMIZATION;

ON-CHIP INDUCTANCE; POWER DELAY PRODUCT; PROPAGATION DELAYS; REPEATER INSERTION; TRANSIENT POWER DISSIPATION; WIRE SIZING;

TELECOMMUNICATION REPEATERS;

EID: 9644295699     PISSN: 01679260     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.vlsi.2004.04.001     Document Type: Article

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