Repeater insertion in deep sub-micron CMOS: Ramp-based analytical model and placement sensitivity analysis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages III-766-III-769

  Nalamalpu, Ankireddy ^a   Burleson, Wayne ^a  

^a University of Massachusetts   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; MATHEMATICAL MODELS; SENSITIVITY ANALYSIS;

RAMP-BASED ANALYTICAL MODEL;

INTEGRATED CIRCUIT LAYOUT;

EID: 0033699061     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.856173     Document Type: Article

References (10)

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