Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertion

Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

Volumn , Issue , 2000, Pages 167-172

  Venkatesan, Raguraman ^a   Davis, Jeffrey A ^a   Bowman, Keith A ^a   Meindl, James D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; LOGIC DESIGN; TELECOMMUNICATION REPEATERS;

MACROCELLS; MULTILEVEL INTERCONNECT ARCHITECTURES; OPTIMAL REPEATER INSERTION;

INTERCONNECTION NETWORKS;

EID: 0033656193     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/344166.344568     Document Type: Article

References (12)