A practical approach to DSM repeater insertion: Satisfying delay constraints while minimizing area and power

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 2001, Pages 152-156

  Nalamalpu, Ankireddy ^a   Burleson, Wayne ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF MASSACHUSETTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER AIDED DESIGN; MOSFET DEVICES; VLSI CIRCUITS;

DELAY CONSTRAINTS; POWER DISSIPATION;

TELECOMMUNICATION REPEATERS;

EID: 0034771119     PISSN: 10630988     EISSN: None     Source Type: Journal    
DOI: 10.1109/ASIC.2001.954689     Document Type: Article

References (13)

1. Optimal interconnection circuits for VLSI
2. Parallel regeneration of interconnections in VLSI & ULSI circuits
3. Optimal methods of driving interconnections in VLSI circuits
4. CMOS circuit speed and buffer optimization
5. Repeater design to reduce delay and power in resistive interconnect
6. Alpha-power law MOSFET model and its applications to CMOS inverter delay and other formulas
7. Repeater insertion in deep sub-micron CMOS: Ramp-based analytical model and placement sensitivity analysis
8. Modeling and simulation of insulated gate field-effect transistor switching circuits
9. Getting to the bottom of deep sub-micron II: A global paradigm
10. Statistical estimation of short-circuit power in VLSI systems
11. Modeling the CMOS short-circuit power dissipation
12. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits