Tuning Strategies for Global Interconnects in High-Performance Deep-Submicron ICs

VLSI Design

Volumn 10, Issue 1, 1999, Pages 21-34

  Kahng, Andrew B ^a,d,i,j,k,l   Muddu, Sudhakar ^{b,c,d,e,f,g,h}   Sarto, Egino ^b,e,m,n  

^a University of California   (United States)

^b HEWLETT PACKARD ENTERPRISE   (United States)

^c INDIAN INSTITUTE OF TECHNOLOGY MADRAS   (India)

^d UNIVERSITY OF CALIFORNIA   (United States)

^e INTEL CORPORATION   (United States)

^f IBM T J WATSON RESEARCH CENTER   (United States)

^g LUCENT TECHNOLOGIES   (United States)

^h VLSI CAD Group

ⁱ HARVARD COLLEGE   (United States)

^j UNIVERSITY OF CALIFORNIA   (United States)

^k ULCA   (United States)

^l CADENCE DESIGN SYSTEMS   (United States)

^m UNIVERSITY OF BRASILIA   (Brazil)

ⁿ STANFORD UNIVERSITY   (United States)

more..

Author keywords

Interconnect delay analysis; Interconnects; Repeater insertion; Scaling; Shielding; Signal integrity; Tuning; Wire pitch

Indexed keywords

EID: 0013059687     PISSN: 1065514X     EISSN: None     Source Type: Journal    
DOI: 10.1155/1999/38974     Document Type: Article

References (16)

1. Alpert, C. J. and Devgan, A., "Wire Segmenting for Improved Buffer Insertion", Proc. Design Automation Conf., June 1997, pp. 588-593.
2. Cong, J., He, L., Kahng, A. B., Noice, D., Shirali, N. and Yen, S. H.-C., "Analysis and Justification of a Simple, Practical 2 1/2-D Capacitance Extraction Methodology", Proc. Design Automation Conference, June 1997.
3. Dartu, F. and Pileggi, L. (1997). "Calculating Worst-Case Gate Delays Due to Dominant Capacitance Coupling", Proc. ACM/IEEE Design Automation Conf., pp. 46-51.
4. Deutsch, A., Kopcsay, G. V., Surovic, C. W., Rubin, B. J., Terman, L. M., Dunne, R. P. and Gallo, T., "Modeling and Characterization of Long On-chip Interconnections for High-Performance Microprocessors", final report, ARPA HSCD Contract C-556003, September 1995. Also appeared In: IBM Journal of Research and Development, 39(5), Sept. 1995, 547-567.
5. Fisher, P. D., "Clock Cycle Estimations for Future Microprocessor Generations", Proc. IEEE Innovative Systems in Silicon, Austin, October 1997.
6. Gwennap, L., "IC Vendors Prepare for 0.25-Micron Leap", Microprocessor Report, September 16, 1996, pp. 11-15.
7. Gwennap, L., "IC Makers Confront RC Limitations", Microdesign Resources Microprocessor Report, August 4, 1997, pp. 14-18.
8. Kahng, A. B. and Muddu, S., $Effcient gate Delay Modeling for Large Interconnect Loads$, Proc. IEEE Multi-Chip Module Conf., Feb. 1996, pp. 202-207.
9. LaPotin, D. P., Ghoshal, U., Chiprout, E. and Nassif, S. R., "Physical Design Challenges for Performance", International Symposium on Physical Design, April 1997, pp. 225-226.
10. Meindl, J., "GigaScale Integration: 'Is the Sky the Limit'?", keynote presentation slides, Hot Chips IX, Stanford, CA, August 25-26, 1997.
11. Oh, S.-Y., Chang, K.-J., Chang, N. and Lee, K., "Interconnect modeling and design in high-speed VLSI/ ULSI systems", Proc. International Conference on Computer Design: VLSI in Computers and Processors, October 1992, pp. 184-189.
12. Rahmat, K., Nakagawa, O. S., Oh, S.-Y., and Moll, J. (1995). "A Scaling Scheme for Interconnect in Deep-Submicron Processes", Intl. Electron Devices Meeting. Technical Digest, pp. 245-248.
13. Scheffer, L., "A Roadmap of CAD Tool Changes for Submicron Interconnect Problems", International Symposium on Physical Design, April 1997, pp. 104-109.
14. Sechler, R. F., "Interconnect design with VLSI CMOS", IBM Journal of Research and Development, Jan.-March 1995, pp. 23-31.
15. Semiconductor Industry Association, National Technology Roadmap for Semiconductors, December 1997.
16. Sylvester, D. and Keutzer, K. (1998). "Getting to the Bottom of Deep-Submicron", Proc. IEEE Intl. Conference on Computer-Aided Design.