On-chip multi-GHz clocking with transmission lines

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2000, Pages 366-367

  Mizuno, M ^a   Anjo, K ^a   Sumi, Y ^a   Wakabayashi, H ^a   Mogami, T ^a   Horiuchi, T ^a   Yamashina, M ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DIELECTRIC LOSSES; ELECTRIC DELAY LINES; ELECTRIC IMPEDANCE; ELECTRIC LINES; ELECTROMAGNETIC WAVES; MICROSTRIP LINES; SIGNAL INTERFERENCE; SIGNAL RECEIVERS;

LOCAL-CLOCKING NETWORKS;

LSI CIRCUITS;

EID: 0034428342     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Clocking design and analysis for a 600MHz alpha microprocessor
2. High-speed signal propagation on lossy transmission lines
3. On-chip interconnects - Giga hertz and beyond