Inductance and capacitance analytic formulas for VLSI interconnects

Electronics Letters

Volumn 32, Issue 11, 1996, Pages 996-997

  Delorme, N ^a   Belleville, M ^a   Chilo, J ^b  

^a CEA LETI   (France)

^b CNRS   (France)

Author keywords

Integrated circuit design; VLSI

Indexed keywords

CAPACITANCE; COMPUTER AIDED DESIGN; COMPUTER SIMULATION; CROSSTALK; DIGITAL INTEGRATED CIRCUITS; ELECTRIC CONDUCTORS; ELECTRIC RESISTANCE; ELECTRIC WIRING; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MONOLITHIC MICROWAVE INTEGRATED CIRCUITS; MULTICHIP MODULES;

CROSSTALK NOISE; INTERCONNECT WIRINGS; RISE TIMES;

VLSI CIRCUITS;

EID: 0030143091     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19960689     Document Type: Article

References (7)

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