Noise-constrained interconnect optimization for nanometer technologies

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  Elgamel, Mohamed A ^a   Tharmalingam, Kannan S ^a   Bayoumi, Magdy A ^a  

^a University of Louisiana at Lafayette   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CROSSTALK; OPTIMIZATION; SPURIOUS SIGNAL NOISE;

INTERCONNECT OPTIMIZATION;

INTERCONNECTION NETWORKS;

EID: 0038081394     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (13)

1. A. B. Kahng and S. Muddu, "An Analytical Delay Model for RLC Interconnects," IEEE Trans. On Computer-Aided-Design Integrated Circuits and Systems, vol. 16, no. 12, pp. 1507-1514, December 1997.
2. A. P. Chandrakasan et al., "Design of Portable Systems," in IEEE Custom Integrated Circuit Conference, pp. 259-266, 1994.
3. A. R. Conn, R. A. Haring, C. Visweswariah, "Noise Consideration in Circuit Optimization," in ICCAD98, 1998.
4. HSPICE 2000.4 release document.
5. K. Soumyanath, S. Borkar, C.Zhou, and B.A. Boechel, "Accurate On-chip Interconnect Evaluation: A time-domain Technique," IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 623-631, May 1999.
6. Lauren Hui Chen, Malgorzata Marek-Sadowska, "Closed-Form Crosstalk Noise Metrics for Physical Design Applications," in proc. The 2002 Design, Automation and Test in Europe Conference and Exhibition (DATE'02), pp. 1-8, March 2002.
7. M. Kuhlmann and S. S. Sapatnekar, "Exact and Efficient Crosstalk Estimation," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 20, no. 7, pp. 858-866, July 2001.
8. th IEEE MWSCAS, August 2002.
9. Mohamed Elgamel, Tarek Darwish, Magdy Bayoumi, "Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops," IEEE annual symposium on VLSI, ISVLSI 2002, pp. 89-94, 2002.
10. T. Sakurai, "Closed-form Expression for Interconnect Delay, Coupling, and Crosstalk in VLSI's," IEEE Trans. Electron devices, vol. 40, no. 1, pp. 118-124, Jan. 1993.
11. TEM waves at http://www.tpup.com/neets/book10
12. The international technology roadmap for semiconductors, http://public.itrs.net/files/1999_SIA_Roadmap/Int.pdf.
13. Woojin Jin et al., "Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuits Interconnects," IEICE Trans. Electron, Vol. E83-c, No. 5, pp. 728-735, May 2000.