High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 15, Issue 9, 1996, Pages 1106-1118

  Zhu, Qing ^a   Dai, Wayne W M ^b  

^a INTEL CORPORATION   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRITICAL PATH ANALYSIS; ELECTRIC CONNECTORS; INTEGRATED CIRCUIT LAYOUT; ITERATIVE METHODS; LAGRANGE MULTIPLIERS; LEAST SQUARES APPROXIMATIONS; MATHEMATICAL MODELS; MINIMIZATION OF SWITCHING NETS; OPTIMIZATION; SYNCHRONIZATION; VLSI CIRCUITS;

CLOCK ROUTING; CLOCK SKEW; GAUSS-MARQUARDT LEAST SQUARE MINIMIZATION METHOD; PATH DELAY BALANCE;

DELAY CIRCUITS;

EID: 0030246821     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/43.536716     Document Type: Article

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