Delay and power expressions characterizing a CMOS inverter driving an RLC load

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2000, Pages

  Tang, Kevin T ^a   Friedman, Eby G ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED NETWORK ANALYSIS; COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; INDUCTANCE MEASUREMENT; INTEGRATED CIRCUIT LAYOUT; MICROPROCESSOR CHIPS; SHORT CIRCUIT CURRENTS; VOLTAGE CONTROL;

ON-CHIP PARASITIC INDUCTANCE; SOFTWARE PACKAGE SPICE;

CMOS INTEGRATED CIRCUITS;

EID: 0033698628     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2000.856052     Document Type: Conference Paper

References (10)