Repeater design to reduce delay and power in resistive interconnect

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 45, Issue 5, 1998, Pages 607-616

  Adler, Victor ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

Buffer insertion; Delay optimization; Rc interconnect; Repeaters

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC RESISTANCE; MATHEMATICAL MODELS; SHORT CIRCUIT CURRENTS;

INTERCONNECTION DELAY; RESISTANCE CAPACITANCE (RC) INTERCONNECTS;

BUFFER CIRCUITS;

EID: 0032072770     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.673643     Document Type: Article

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