Minimum repeater count, size, and energy dissipation for gigascale integration (GSI) interconnects

Proceedings of the IEEE 1998 International Interconnect Technology Conference, IITC 1998

Volumn 1998-June, Issue , 1998, Pages 56-58

  Eble, J C ^a   De, V K ^b   Wills, D S ^a   Meindl, J D ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ENERGY DISSIPATION; PRODUCT DESIGN;

CLOCK FREQUENCY; ENERGY DELAY PRODUCT; GIGASCALE INTEGRATION; NOVEL DESIGN; REPEATER INSERTION;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 0038545297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IITC.1998.704750     Document Type: Conference Paper

References (5)

1. J. A. Davis, V. K. De and J. D. Meindl, "Optimal low power interconnect networks, " Sym. VLSI Tech. Digest, pp. 78-79, June 1996.
2. SIA National Technology Roadmap for Semiconductors, 1994.
3. H. B. Bakoglu and J. D. Meindl, "Optimal interconnection circuits for VLSI, " IEEE Trans. on Electron Devices, vol. 32, pp. 903-909, May 1985.
4. B. S. Landman and R. L. Russo, "On a pin versus block relationship for partitions of logic graphs, " IEEE Trans. on Computers, vol. C-20, pp. 1469-1479, Dec. 1971.
5. H. B. Bakoglu, Circuits, Interconnections and Packaging for VLSI, first edition, Reading, MA: Addison Wesley, 1990.