Effective on-chip inductance modeling for multiple signal lines and application on repeater insertion

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn 2001-January, Issue , 2001, Pages 185-190

  Cao, Yu ^a   Huang, Xuejue ^a   Chang, Norman ^b   Lin, Shen ^b   Nakagawa, O Sam ^b   Xie, Weize ^b   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

^b HEWLETT PACKARD LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

INDUCTANCE; TABLE LOOKUP; TELECOMMUNICATION REPEATERS;

COMPUTATION EFFICIENCY; INDUCTANCE EFFECTS; NUMERICAL APPROACHES; ON-CHIP INDUCTANCE; REPEATER INSERTION; SIGNAL INTEGRITY ANALYSIS; STATIC TIMING ANALYSIS; SWITCHING PATTERNS;

MICROSTRIP LINES;

EID: 0037776893     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2001.915225     Document Type: Conference Paper

References (16)

1. International Technology Roadmap for Semiconductors (ITRS), 1999.
2. H. B. Bakoglu, "Circuits, Interconnections, and Packaging for VLSI", Addison-Wesley Pub. Co., 1990.
3. T. Sakurai, "Approximation of Wiring Delay in MOSFET LSI", IEEE Jour. of Solid-State Circuits, Vol. 18, pp. 418-426, Aug. 1983.
4. S. Nakagawa, D. Sylvester, J. G. McBride, and S. Y. Oh, "On-Chip Cross Talk Noise Model for Deep-Submicrometer ULSI Interconnect", HP Journal, pp. 39-45, Aug. 1998.
5. A. Deutsch, et al, "When are Transmission-Line Effects Important for On-Chip Interconnects", IEEE Trans. on Microwave Theory Tech., Vol. 45, pp. 1836-1846, Oct. 1997.
6. A. Deutsch, et al, "The Importance of Inductance and Inductive Coupling for On-Chip Wiring", Proc. of IEEE 6-th Electrical Performance of Electronic Packaging, pp. 53-56, Oct. 1997.
7. C. K. Cheng, J. Lillis, S. Lin, and N. Chang, "Interconnect Analysis and Synthesis", John Wiley & Sons, Inc., 1999.
8. Frederick W. Grover, "Inductance Calculations Working Formulas and Tables", Dover Publications, Inc., 1946.
9. S. Lin, N. Chang, and S. Nakagawa, "Quick On-Chip Self and Mutual-Inductance Screen", International Symposium of Quality Electronic Design (ISQED), Mar. 1999.
10. B. Krauter and L. Pilleggi, "Generation Sparse Partial Inductance Matrices with Guaranteed Stability", Proc. of IEEE ICCAD, pp 45-52, Nov. 1995.
11. A. Kahng, S. Muddu, and E. Sarto, "On Switch Factor Based Analysis of Coupled RC Interconnects", Proc. of DAC, pp. 79-84, Jun, 2000.
12. N. Chang, S. Lin, L. He, S. Nakagawa, and W. Xie, "Clock tree RLC Extraction with Efficient Inductance Modeling", Prod. of DATE, 2000.
13. L. He, N. Chang, S. Lin, and O.S. Nakagawa, "An Efficient Inductance Modeling for On-Chip Interconnects," Proc. of CICC, pp. 457-460, 1999.
14. Y. Cao, X. Huang, D. Sylvester, N. Chang, and C. Hu, "A New Analytical Model for On-Chip RLC Coupling Interconnect", to be published at IEDM, Dec. 2000.
15. Y. I. Ismail, and E. G. Friedman, "Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits", Proc. of DAC, pp. 721-724, Jun. 1999.
16. N. Chang, G. Zavagli, K. Rahmat, J. Ku, J. Wanek, and S.Y. Oh, "Signal Net Optimization via Repeater Insertion and Transistor Sizing", HP Design Tech. Conf., 1997.