Inductive interconnect width optimization for low power

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2003, Pages

  El Moursy, Magdy A ^a   Friedman, Eby G ^a  

^a University of Rochester   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CMOS INTEGRATED CIRCUITS; OPTIMIZATION; SHORT CIRCUIT CURRENTS;

INDUCTIVE INTERCONNECTS;

LARGE SCALE SYSTEMS;

EID: 0037744582     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)

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2. C. J. Anderson et al., "Physical Design of a Fourth-Generation POWER GHz Microprocessor," Proceedings of the IEEE International Solid-State Circuits Conference, pp. 232-233, February 2001.
3. J. J. Cong, K. Leung, and D. Zhou, "Performance-Driven Interconnect Design Based on Distributed RC Delay Model," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 14, No. 3, pp. 321-336, March 1995.
4. Q. Zhu and W. M. Dai, "High-Speed Clock Network Sizing Optimization Based on Distributed RC and Lossy RLC Interconnect Models," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 15, No. 9, pp. 1106-1118, September 1996.
5. J. Lillis, C. Cheng, and T. Y. Lin, "Optimal Wire Sizing and Buffer Insertion for Low Power and a Generalized Delay Model," IEEE Journal of Solid State Circuits, Vol. 31, No. 3, pp. 437-447, March 1996.
6. M. A. El-Moursy and E. G. Friedman, "Optimizing Inductive Interconnect for Low Power," Proceedings of the International Workshop on System-on-Chip for Real-Time Applications, pp. 206-216, July 2002.
7. N. Delorme, M. Belleville, and J. Chilo, "Inductance and Capacitance Analytic Formulas for VLSI Interconnects," Electronics Letters, Vol. 32, No, 11, pp. 996-997, May 1996.
8. Y. Lu, K. Banerjee, M. Celik and R. W. Dutton, "A Fast Analytical Technique for Estimating the Bounds of On-Chip Clock Wire Inductance," Proceedings of the IEEE Custom Integrated Circuits Conference, pp. 241-244, May 2001.