200-MHz superscalar RISC microprocessor

IEEE Journal of Solid-State Circuits

Volumn 31, Issue 11, 1996, Pages 1675-1685

  Vasseghi, Nader ^a,b,c,d,e   Yeager, Kenneth ^a,f,g   Sarto, Egino ^a   Seddighnezhad, Mahdi ^a  

^a HEWLETT PACKARD ENTERPRISE   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

^c UNIVERSITY OF SOUTHAMPTON   (United Kingdom)

^d Optoelectronics Division

^e ADVANCED MICRO DEVICES   (United States)

^f MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

^g MIPS Technologies Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSOCIATIVE STORAGE; BUFFER STORAGE; CMOS INTEGRATED CIRCUITS; DATA ACQUISITION; DECODING; INTEGRATED CIRCUIT LAYOUT; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; SEMICONDUCTOR STORAGE; TRANSISTORS;

MEMORY LATENCY; POWER CONSUMPTION;

MICROPROCESSOR CHIPS;

EID: 0030284493     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/jssc.1996.542312     Document Type: Article

References (8)

1. MIPS R10000 Microprocessor User's Manual, June 1995.
2. N. Vasseghi et al., "200 MHz superscalar RISC processor circuit design issues," in ISSCC '96.
3. K. Yeager, "MIPS R10000 superscalar microprocessor," IEEE Micro Mag., Apr. 1996.
4. P. J. Song and G. De Micheli, "Circuit and architecture trade-offs for high speed multiplication," IEEE J. Solid-State Circuits, vol. 26, pp. 1184-1198, Sept. 1991.
5. S. Mirapuri, M. Woodacre, and N. Vasseghi, "The mips R4000 processor," IEEE Micro Mag., Apr. 1992.
6. J. L. Hennessey and D. A. Patterson, Computer Architecture: A Qualitative Approach. San Mateo, CA: Morgan Kaufmann, 1990.
7. Spec95 http://www.specbench.org.
8. MIPS Technologies Inc., press release Jan. 18, 1996, http.//www.sgi.com.