Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 9, Issue 6, 2001, Pages 899-912

  Venkatesan, Raguraman ^a,b   Davis, Jeffrey A ^a,b   Bowman, Keith A ^a,b   Meindl, James D ^a,b  

^a IEEE   (United States)

^b GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

Interconnections; Modeling; Multilevel systems; Repeaters; System analysis and design; System optimization; System level interconnect prediction (SLIP); Wire length distribution

Indexed keywords

GIGASCALE INTEGRATION (GSI);

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; MICROPROCESSOR CHIPS; SYSTEMS ANALYSIS;

VLSI CIRCUITS;

EID: 0035704586     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.974903     Document Type: Article

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