-
1
-
-
0033279861
-
Figures of merit to characterize the importance of on-chip inductance
-
Dec.
-
Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Figures of merit to characterize the importance of on-chip inductance," IEEE Trans. VLSI Syst., vol. 7, pp. 442-449, Dec. 1999.
-
(1999)
IEEE Trans. VLSI Syst.
, vol.7
, pp. 442-449
-
-
Ismail, Y.I.1
Friedman, E.G.2
Neves, J.L.3
-
2
-
-
0035704577
-
Exploiting on-chip inductance in high speed clock distribution networks
-
Dec.
-
_, "Exploiting on-chip inductance in high speed clock distribution networks," IEEE Trans. VLSI Syst., vol. 9, pp. 963-973, Dec. 2001.
-
(2001)
IEEE Trans. VLSI Syst.
, vol.9
, pp. 963-973
-
-
-
3
-
-
0033891230
-
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
-
Apr.
-
Y. I. Ismail and E. G. Friedman, "Effects of inductance on the propagation delay and repeater insertion in VLSI circuits," IEEE Trans. VLSI Syst., vol. 8, pp. 195-206, Apr. 2000.
-
(2000)
IEEE Trans. VLSI Syst.
, vol.8
, pp. 195-206
-
-
Ismail, Y.I.1
Friedman, E.G.2
-
4
-
-
0035327739
-
Repeater insertion in tree structured inductive interconnect
-
May
-
Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Repeater insertion in tree structured inductive interconnect," IEEE Trans. Circuits Syst., vol. 48, pp. 471-481, May 2001.
-
(2001)
IEEE Trans. Circuits Syst.
, vol.48
, pp. 471-481
-
-
Ismail, Y.I.1
Friedman, E.G.2
Neves, J.L.3
-
5
-
-
0032071753
-
High-performance microprocessor design
-
May
-
P. E. Gronowski et al., "High-performance microprocessor design," IEEE J. Solid-State Circuits, vol. 33, pp. 676-686, May 1998.
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, pp. 676-686
-
-
Gronowski, P.E.1
-
6
-
-
0035054909
-
Physical design of a fourth-generation POWER GHz microprocessor
-
Feb.
-
C. J. Anderson et al., "Physical design of a fourth-generation POWER GHz microprocessor," in Proc. IEEE Int. Solid-State Circuits Conf., Feb. 2001, pp. 232-233.
-
(2001)
Proc. IEEE Int. Solid-state Circuits Conf.
, pp. 232-233
-
-
Anderson, C.J.1
-
7
-
-
0026955423
-
A 200-Mhz 64-b dual-issue CMOS microprocessor
-
Nov.
-
D. W. Dobberpuhl et al., "A 200-Mhz 64-b dual-issue CMOS microprocessor," IEEE J. Solid State Circuits, vol. SC-27, pp. 1555-1565, Nov. 1992.
-
(1992)
IEEE J. Solid State Circuits
, vol.SC-27
, pp. 1555-1565
-
-
Dobberpuhl, D.W.1
-
8
-
-
0028553463
-
Dynamically-wiresized Elmore-based routing constructions
-
May
-
T. D. Hodes, B. A. McCoy, and G. Robins, "Dynamically-wiresized Elmore-based routing constructions," in Proc. IEEE Int. Symp. Circuits and Systems, vol. I, May 1994, pp. 463-466.
-
(1994)
Proc. IEEE Int. Symp. Circuits and Systems
, vol.1
, pp. 463-466
-
-
Hodes, T.D.1
McCoy, B.A.2
Robins, G.3
-
10
-
-
0028560876
-
RC interconnect optimization under the Elmore delay model
-
June
-
S. S. Sapatnekar, "RC interconnect optimization under the Elmore delay model," in Proc. IEEE/ACM Design Automation Conf., June 1994, pp. 387-391.
-
(1994)
Proc. IEEE/ACM Design Automation Conf.
, pp. 387-391
-
-
Sapatnekar, S.S.1
-
11
-
-
0029264252
-
Optimal wiresizing under Elmore delay model
-
Mar.
-
J. J. Cong and K. Leung, "Optimal wiresizing under Elmore delay model," IEEE Trans. Computer-Aided Design, vol. 14, pp. 321-336, Mar. 1995.
-
(1995)
IEEE Trans. Computer-aided Design
, vol.14
, pp. 321-336
-
-
Cong, J.J.1
Leung, K.2
-
12
-
-
0027206875
-
Performance-driven interconnect design based on distributed RC delay model
-
June
-
J. J. Cong, K. Leung, and D. Zhou, "Performance-driven interconnect design based on distributed RC delay model," in Proc. IEEE Design Automation Conf., June 1993, pp. 606-611.
-
(1993)
Proc. IEEE Design Automation Conf.
, pp. 606-611
-
-
Cong, J.J.1
Leung, K.2
Zhou, D.3
-
13
-
-
0032759314
-
Spec-based repeater insertion and wire sizing for on-chip interconnect
-
Jan.
-
C. P. Chen and N. Menezes, "Spec-based repeater insertion and wire sizing for on-chip interconnect," in Proc. IEEE Int. Conf. VLSI Design, Jan. 1999, pp. 476-483.
-
(1999)
Proc. IEEE Int. Conf. VLSI Design
, pp. 476-483
-
-
Chen, C.P.1
Menezes, N.2
-
14
-
-
0028728396
-
Simultaneous driver and wire sizing for performance and power optimization
-
Dec.
-
J. J. Cong and C.-K. Koh, "Simultaneous driver and wire sizing for performance and power optimization," IEEE Trans. VLSI Syst., vol. 2, pp. 408-425, Dec. 1994.
-
(1994)
IEEE Trans. VLSI Syst.
, vol.2
, pp. 408-425
-
-
Cong, J.J.1
Koh, C.-K.2
-
15
-
-
0029516536
-
Optimal wire sizing and buffer insertion for low power and a generalized delay model
-
Nov.
-
J. Lillis, C.-K. Cheng, and T.-T. Y. Lin, "Optimal wire sizing and buffer insertion for low power and a generalized delay model," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1995, pp. 138-143.
-
(1995)
Proc. IEEE Int. Conf. Computer-aided Design
, pp. 138-143
-
-
Lillis, J.1
Cheng, C.-K.2
Lin, T.-T.Y.3
-
16
-
-
0029771320
-
A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies
-
February
-
T. Xue, E. S. Kuh, and Q. Yu, "A sensitivity-based wiresizing approach to interconnect optimization of lossy transmission line topologies," in Proc. IEEE Multi-Chip Module Conf., February 1996, pp. 117-121.
-
(1996)
Proc. IEEE Multi-chip Module Conf.
, pp. 117-121
-
-
Xue, T.1
Kuh, E.S.2
Yu, Q.3
-
17
-
-
0030246821
-
High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models
-
Sept.
-
Q. Zhu and W. M. Dai, "High-speed clock network sizing optimization based on distributed RC and lossy RLC interconnect models," IEEE Trans. Computer-Aided Design, vol. 15, pp. 1106-1118, Sept. 1996.
-
(1996)
IEEE Trans. Computer-aided Design
, vol.15
, pp. 1106-1118
-
-
Zhu, Q.1
Dai, W.M.2
-
18
-
-
0027878190
-
Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models
-
Nov.
-
Q. Zhu, W. M. Dai, and J. G. Xi, "Optimal sizing of high-speed clock networks based on distributed RC and lossy transmission line models, " in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1993, pp. 628-633.
-
(1993)
Proc. IEEE Int. Conf. Computer-aided Design
, pp. 628-633
-
-
Zhu, Q.1
Dai, W.M.2
Xi, J.G.3
-
19
-
-
0031386317
-
Interconnect layout optimization under higher-order RLC model
-
Nov.
-
J. J. Cong and C.-K. Koh, "Interconnect layout optimization under higher-order RLC model," in Proc. IEEE Int. Conf. Computer-Aided Design, Nov. 1997, pp. 713-720.
-
(1997)
Proc. IEEE Int. Conf. Computer-aided Design
, pp. 713-720
-
-
Cong, J.J.1
Koh, C.-K.2
-
20
-
-
0036045685
-
A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters
-
May
-
P. Heydari, S. Abbaspour, and M. Pedram, "A comprehensive study of energy dissipation in lossy transmission lines driven by CMOS inverters," in Proc. IEEE Custom Integrated Circuits Conf., May 2002, pp. 517-520.
-
(2002)
Proc. IEEE Custom Integrated Circuits Conf.
, pp. 517-520
-
-
Heydari, P.1
Abbaspour, S.2
Pedram, M.3
-
21
-
-
0036292953
-
Energy dissipation modeling of lossy transmission lines driven by CMOS inverters
-
May
-
P. Heydari, "Energy dissipation modeling of lossy transmission lines driven by CMOS inverters," in Proc. IEEE Int. Symp. Circuits Systems, vol. IV, May 2002, pp. 309-312.
-
(2002)
Proc. IEEE Int. Symp. Circuits Systems
, vol.4
, pp. 309-312
-
-
Heydari, P.1
-
22
-
-
0034841277
-
An interconnect energy model considering coupling effects
-
June
-
T. Uchino and J. Cong, "An interconnect energy model considering coupling effects," in Proc. IEEE. Design Automation Conf., June 2001, pp. 555-558.
-
(2001)
Proc. IEEE. Design Automation Conf.
, pp. 555-558
-
-
Uchino, T.1
Cong, J.2
-
24
-
-
0038453783
-
Optimizing inductive interconnect for low power
-
W. Badawy and G. A. Jullien, Eds. Norwell, MA: Kluwer
-
_, "Optimizing inductive interconnect for low power," in System-on-Chip for Real-Time Applications, W. Badawy and G. A. Jullien, Eds. Norwell, MA: Kluwer, 2003, pp. 380-391.
-
(2003)
System-on-chip for Real-time Applications
, pp. 380-391
-
-
-
25
-
-
0037744582
-
Inductive interconnect width optimization for low power
-
May
-
_, "Inductive interconnect width optimization for low power," in Proc. IEEE Int. Symp. Circuits Systems, May 2003, pp. 5.273-5.276.
-
(2003)
Proc. IEEE Int. Symp. Circuits Systems
-
-
-
26
-
-
12344252501
-
Power characteristics of inductive interconnect
-
Dec.
-
_, "Power characteristics of inductive interconnect," in Proc. IEEE Int. Conf. Electronics, Circuits, Systems, vol. II, Dec. 2003, pp. 499-502.
-
(2003)
Proc. IEEE Int. Conf. Electronics, Circuits, Systems
, vol.2
, pp. 499-502
-
-
-
28
-
-
0032025472
-
Propagation delay and short-circuit power dissipation modeling of the CMOS inverter
-
Mar.
-
L. Bisdounis, S. Nikolaidis, and O. Koufopavlou, "Propagation delay and short-circuit power dissipation modeling of the CMOS inverter," IEEE Trans. Circuits Syst. I, vol. 45, pp. 259-270, Mar. 1998.
-
(1998)
IEEE Trans. Circuits Syst. I
, vol.45
, pp. 259-270
-
-
Bisdounis, L.1
Nikolaidis, S.2
Koufopavlou, O.3
-
29
-
-
0032630123
-
Dynamic and short-circuit power of CMOS gates driving lossless transmission lines
-
Aug.
-
Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Dynamic and short-circuit power of CMOS gates driving lossless transmission lines," IEEE Trans. Circuits Syst. I, vol. 46, pp. 950-961, Aug. 1999.
-
(1999)
IEEE Trans. Circuits Syst. I
, vol.46
, pp. 950-961
-
-
Ismail, Y.I.1
Friedman, E.G.2
Neves, J.L.3
-
30
-
-
0033698628
-
Delay and power expressions characterizing a CMOS inverter driving an RLC load
-
May
-
K. T. Tang and E. G. Friedman, "Delay and power expressions characterizing a CMOS inverter driving an RLC load," in Proc. IEEE Int. Symp. Circuits Syst., vol. III, May 2000, pp. 283-286.
-
(2000)
Proc. IEEE Int. Symp. Circuits Syst.
, vol.3
, pp. 283-286
-
-
Tang, K.T.1
Friedman, E.G.2
-
31
-
-
0030143091
-
Inductance and capacitance analytic formulas for VLSI interconnects
-
May
-
N. Delorme, M. Belleville, and J. Chilo, "Inductance and capacitance analytic formulas for VLSI interconnects," Electron. Lett., vol. 32, no. 11, pp. 996-997, May 1996.
-
(1996)
Electron. Lett.
, vol.32
, Issue.11
, pp. 996-997
-
-
Delorme, N.1
Belleville, M.2
Chilo, J.3
-
32
-
-
0001691745
-
The self and mutual inductances of linear conductors
-
Jan.
-
E. B. Rosa, "The self and mutual inductances of linear conductors," Bull. Nat. Bur. Stand., vol. 4, no. 2, pp. 301-344, Jan. 1908.
-
(1908)
Bull. Nat. Bur. Stand.
, vol.4
, Issue.2
, pp. 301-344
-
-
Rosa, E.B.1
-
33
-
-
0034835833
-
A fast analytical technique for estimating the bounds of on-chip clock wire inductance
-
May
-
Y. Lu, K. Banerjee, M. Celik, and R. W. Dutton, "A fast analytical technique for estimating the bounds of on-chip clock wire inductance," in Proc. IEEE Custom Integrated Circuits Conf., May 2001, pp. 241-244.
-
(2001)
Proc. IEEE Custom Integrated Circuits Conf.
, pp. 241-244
-
-
Lu, Y.1
Banerjee, K.2
Celik, M.3
Dutton, R.W.4
-
34
-
-
0032206398
-
Clocking design and analysis for a 600-MHz alpha microprocessor
-
Nov.
-
D. W. Bailey and B. J. Benschneider, "Clocking design and analysis for a 600-MHz alpha microprocessor," IEEE J. Solid-State Circuits, vol. 33, pp. 1627-1633, Nov. 1998.
-
(1998)
IEEE J. Solid-state Circuits
, vol.33
, pp. 1627-1633
-
-
Bailey, D.W.1
Benschneider, B.J.2
-
35
-
-
0030284493
-
200-MHz superscalar RISC microprocessor
-
Nov.
-
N. Vasseghi, K. Yeager, E. Sarto, and M. Seddighnezhad, "200-MHz superscalar RISC microprocessor," IEEE J. Solid-State Circuits, vol. 31, pp. 1675-1686, Nov. 1996.
-
(1996)
IEEE J. Solid-state Circuits
, vol.31
, pp. 1675-1686
-
-
Vasseghi, N.1
Yeager, K.2
Sarto, E.3
Seddighnezhad, M.4
-
36
-
-
0034317347
-
Clock generation and distribution for the first IA-64 microprocessor
-
Nov.
-
S. Tam et al., "Clock generation and distribution for the first IA-64 microprocessor," IEEE J. Solid-State Circuits, vol. 35, pp. 1545-1552, Nov. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, pp. 1545-1552
-
-
Tam, S.1
-
37
-
-
0037347427
-
Loop-based interconnect modeling and optimization approach for multigigahertz clock network design
-
Mar.
-
X. Huang et al., "Loop-based interconnect modeling and optimization approach for multigigahertz clock network design," IEEE J. Solid-State Circuits, vol. 38, pp. 457-463, Mar. 2003.
-
(2003)
IEEE J. Solid-state Circuits
, vol.38
, pp. 457-463
-
-
Huang, X.1
-
38
-
-
0031349694
-
An analytical delay model for RLC interconnects
-
Dec.
-
A. B. Kahng and S. Muddu, "An analytical delay model for RLC interconnects," IEEE Trans. Computer-Aided Design, vol. 16, pp. 1507-1514, Dec. 1997.
-
(1997)
IEEE Trans. Computer-aided Design
, vol.16
, pp. 1507-1514
-
-
Kahng, A.B.1
Muddu, S.2
-
39
-
-
0020797359
-
Approximation of wiring delay in MOSFET LSI
-
Aug.
-
T. Sakurai, "Approximation of wiring delay in MOSFET LSI," IEEE J. Solid-State Circuits, vol. SC-18, pp. 418-426, Aug. 1983.
-
(1983)
IEEE J. Solid-state Circuits
, vol.SC-18
, pp. 418-426
-
-
Sakurai, T.1
-
40
-
-
0027202967
-
Performance driven MCM routing using a second order RLC tree delay model
-
Jan.
-
M. Sriram and S. M. Kang, "Performance driven MCM routing using a second order RLC tree delay model," in Proc. IEEE Int. Conf. Wafer Scale Integration, Jan. 1993, pp. 262-267.
-
(1993)
Proc. IEEE Int. Conf. Wafer Scale Integration
, pp. 262-267
-
-
Sriram, M.1
Kang, S.M.2
-
41
-
-
0036474096
-
DTT: Direct truncation of the transfer function - An alternative to moment matching for tree structured interconnect
-
Feb.
-
Y. I. Ismail and E. G. Friedman, "DTT: Direct truncation of the transfer function - An alternative to moment matching for tree structured interconnect," IEEE Trans. Computer-Aided Design, vol. 21, pp. 131-144, Feb. 2002.
-
(2002)
IEEE Trans. Computer-aided Design
, vol.21
, pp. 131-144
-
-
Ismail, Y.I.1
Friedman, E.G.2
-
42
-
-
0033881978
-
Equivalent Elmore delay for RLC trees
-
Jan.
-
Y. I. Ismail, E. G. Friedman, and J. L. Neves, "Equivalent Elmore delay for RLC trees," IEEE Trans. Computer-Aided Design, vol. 19, pp. 83-97, Jan. 2000.
-
(2000)
IEEE Trans. Computer-aided Design
, vol.19
, pp. 83-97
-
-
Ismail, Y.I.1
Friedman, E.G.2
Neves, J.L.3
-
43
-
-
0027225034
-
Propagation delay in RLC interconnection networks
-
May
-
D. S. Gao and D. Zhou, "Propagation delay in RLC interconnection networks," in Proc. IEEE Int. Symp. Circuits Systems, May 1993, pp. 2125-2128.
-
(1993)
Proc. IEEE Int. Symp. Circuits Systems
, pp. 2125-2128
-
-
Gao, D.S.1
Zhou, D.2
-
44
-
-
0026138465
-
A simple MOSFET model for circuit analysis
-
Apr.
-
T. Sakurai and A. R. Newton, "A simple MOSFET model for circuit analysis," IEEE Trans. Electron Devices, vol. 38, pp. 887-894, Apr. 1991.
-
(1991)
IEEE Trans. Electron Devices
, vol.38
, pp. 887-894
-
-
Sakurai, T.1
Newton, A.R.2
-
45
-
-
0032638670
-
A time-domain model power dissipation of CMOS buffer driving lossy lines
-
June
-
G. Cappuccino and G. Cocorullo, "A time-domain model power dissipation of CMOS buffer driving lossy lines," Electron. Lett., vol. 35, no. 12, pp. 959-960, June 1999.
-
(1999)
Electron. Lett.
, vol.35
, Issue.12
, pp. 959-960
-
-
Cappuccino, G.1
Cocorullo, G.2
-
46
-
-
0035183802
-
Performance optimization by wire and buffer sizing under the transmission line model
-
Nov.
-
T.-C. Chen, S.-R. Pan, and Y.-W. Chang, "Performance optimization by wire and buffer sizing under the transmission line model," in Proc. IEEE Int. Conf. Computer Design, Nov. 2001, pp. 192-197.
-
(2001)
Proc. IEEE Int. Conf. Computer Design
, pp. 192-197
-
-
Chen, T.-C.1
Pan, S.-R.2
Chang, Y.-W.3
-
47
-
-
0031685852
-
Calculation of ramp response of lossy transmission lines using two-port network functions
-
Apr.
-
P. Heydari and M. Pedram, "Calculation of ramp response of lossy transmission lines using two-port network functions," in Proc. ACM Int. Symp. Physical Design, Apr. 1998, pp. 152-157.
-
(1998)
Proc. ACM Int. Symp. Physical Design
, pp. 152-157
-
-
Heydari, P.1
Pedram, M.2
-
48
-
-
0028747088
-
Optimal design of self-damped lossy transmission lines for multichip modules
-
Oct.
-
J. Wang and W. Dai, "Optimal design of self-damped lossy transmission lines for multichip modules," in Proc. IEEE Int. Conf. Computer Design, Oct. 1994, pp. 594-598.
-
(1994)
Proc. IEEE Int. Conf. Computer Design
, pp. 594-598
-
-
Wang, J.1
Dai, W.2
|