Background calibration of time-interleaved data converters

Background Calibration of Time-Interleaved Data Converters

Volumn , Issue , 2012, Pages 1-123

  El Chammas, Manar ^a   Murmann, Boris ^b  

^a TEXAS INSTRUMENTS   (United States)

^b Stanford University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG-TO-DIGITAL DATA CONVERTERS; BACKGROUND CALIBRATIONS; BANDWIDTH REQUIREMENT; DATA CONVERTER; SYSTEM ARCHITECTURES; TIME VARYING SIGNAL; TIME-INTERLEAVED; TIME-INTERLEAVING;

ANALOG TO DIGITAL CONVERSION;

EID: 85019670704     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1007/978-1-4614-1511-4     Document Type: Book

References (80)

1. STA, "Serial Attached SCSI - Roadmap," http://www.scsita.org/saslibrary/sas-masterroadmaps/.
2. V. Balan, J. Caroselli, J.-G. Chern, C. Chow, R. Dadi, C. Desai, L. Fang, D. Hsu, P. Joshi, H. Kimura, C. Liu, T.-W. Pan, R. Park, C. You, Y. Zeng, E. Zhang, and F. Zhong, "A 4.8-6. 4-Gb/s Serial Link for Backplane Applications Using Decision Feedback Equalization," IEEE Journal of Solid-State Circuits, vol. 40, no. 9, pp. 1957-1967, Sept. 2005.
3. M. Harwood, N. Warke, R. Simpson, T. Leslie, A. Amerasekera, S. Batty, D. Colman, E. Carr, V. Gopinathan, S. Hubbins, P. Hunt, A. Joy, P. Khandelwal, B. Killips, T. Krause, S. Lytollis, A. Pickering, M. Saxton, D. Sebastio, G. Swanson, A. Szczepanek, T. Ward, J. Williams, R. Williams, and T. Willwerth, "A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2007, pp. 436-591.
4. H. Chung, A. Rylyakov, Z. T. Deniz, J. Bulzacchelli, G.-Y. Wei, and D. Friedman, "A 7.5- GS/s 3.8-ENOB 52-mW Flash ADC with Clock Duty Cycle Control in 65nm CMOS," in VLSI Circuits Symposium, Digest of Technical Papers, June 2009, pp. 268-269.
5. W. Black and D. Hodges, "Time Interleaved Converter Arrays," IEEE Journal of Solid-State Circuits, vol. 15, no. 6, pp. 1022-1029, Dec. 1980.
6. Y.-C. Jenq, "Digital Spectra of Nonuniformly Sampled Signals: Fundamentals and High-Speed Waveform Digitizers," IEEE Transactions on Instrumentation and Measurement, vol. 37, no. 2, pp. 245-251, June 1988.
7. J. Proakis and D. Manolakis, Digital Signal Processing, 3rd ed. Prentice Hall, New Jersey, USA, 1996.
8. A. V. Oppenheim, A. S. Willsky, and S. Hamid, Signals and Systems, 2nd ed. Prentice Hall, New Jersey, USA,1996.
9. N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, "Explicit Analysis of Channel Mismatch Effects in Time-Interleaved ADC Systems," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 48, no. 3, pp. 261-271, March 2001.
10. M. El-Chammas and B. Murmann, "General Analysis on the Impact of Phase-Skew in Time- Interleaved ADCs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 902-910, May 2009.
11. A. Papoulis, Probability, Random Variables, and Stochastic Processes, 3rd ed. McGraw-Hill, New York, 1991.
12. C. Vogel, "The Impact of Combined Channel Mismatch Effects in Time-Interleaved ADCs," IEEE Transactions on Instrumentation and Measurement, vol. 54, no. 1, pp. 415-427, Feb. 2005.
13. N. Da Dalt, M. Harteneck, C. Sandner, and A. Wiesbauer, "On the Jitter Requirements of the Sampling Clock for Analog-to-Digital Converters," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 49, no. 9, pp. 1354-1360, Sept. 2002.
14. S. Louwsma, A. van Tuijl, M. Vertregt, and B. Nauta, "A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 μm CMOS," IEEE Journal of Solid-State Circuits, vol. 43, no. 4, pp. 778-786, Apr. 2008.
15. M. Pelgrom, A. Duinmaijer, and A.Welbers, "Matching Properties ofMOS Transistors," IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
16. A. Agrawal, A. Liu, P. Hanumolu, and G.-Y. Wei, "An 8 × 5 Gb/s Parallel Receiver With Collaborative Timing Recovery," IEEE Journal of Solid-State Circuits, vol. 44, no. 11, pp. 3120-3130, Nov. 2009.
17. S. Gupta, M. Inerfield, and J. Wang, "A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture," IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2650-2657, Dec. 2006.
18. K. Poulton, J. Corcoran, and T. Hornak, "A 1-GHz 6-bit ADC System," IEEE Journal of Solid- State Circuits, vol. 22, no. 6, pp. 962-970, Dec. 1987.
19. S. Jamal, D. Fu, N.-J. Chang, P. Hurst, and S. Lewis, "A 10-b 120-Msample/s Time-Interleaved Analog-to-Digital Converter with Digital Background Calibration," IEEE Journal of Solid- State Circuits, vol. 37, no. 12, pp. 1618-1627, Dec. 2002.
20. T. Laakso, V. Valimaki, M. Karjalainen, and U. Laine, "Splitting the Unit Delay - Tools for Fractional Delay Filter Design," IEEE Signal Processing Magazine, vol. 13, no. 1, pp. 30-60, Jan. 1996.
21. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, "A 20 GS/s 8 b ADC with a 1 MB Memory in 0.18 μm CMOS," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2003, pp. 318-496.
22. D. Camarero, K. Ben Kalaia, J.-F. Naviner, and P. Loumeau, "Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 11, pp. 3676-3687, Dec. 2008.
23. S. Boyd and L. Vandendberghe, Convex Optimization. Cambridge University Press, New York, 2004.
24. W. Root and W. Davenport, An Introduction to the Theory of Random Signals and Noise, 2nd ed. McGraw-Hill, New York, 1958.
25. J. J. Bussgang, "Crosscorrelation Functions of Amplitude-Distorted Gaussian Signals," MIT Research Laboratory of Electronics Technical Reports, no. 216, March 1952.
26. C.-Y. Wang and J.-T. Wu, "A Multiphase Timing-Skew Calibration Technique Using Zero- Crossing Detection," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 6, pp. 1102-1114, June 2009.
27. J. Van Vleck and D. Middleton, "The Spectrum of Clipped Noise," Proceedings of the IEEE, vol. 54, no. 1, pp. 2-19, Jan. 1966.
28. F. Todero, "On Some Bonds Between Autocorrelation and Power Spectra Functions," Proceedings of the IEEE, vol. 56, no. 12, pp. 2170-2171, Dec. 1968.
29. J. McFadden, "The Axis-Crossing Intervals of Random Functions," IRE Transactions on Information Theory, vol. 2, no. 4, pp. 146-150, Dec. 1956.
30. H. Pan and A. Abidi, "Signal Folding in A/D Converters," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 51, no. 1, pp. 3-14, Jan. 2004.
31. R. Van De Plassche and R. Van Der Grift, "A High-Speed 7 Bit A/D Converter," IEEE Journal of Solid-State Circuits, vol. 14, no. 6, pp. 938-943, Dec. 1979.
32. T. Toifl, C.Menolfi, M. Ruegg, R. Reutemann, P. Buchmann, M. Kossel, T.Morf, J.Weiss, and M. Schmatz, "A 22-Gb/s PAM-4 Receiver in 90-nm CMOS SOI Technology," IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 954-965, Apr. 2006.
33. T. Toifl, "Design Techniques for Ultra-Low-Power and Compact Transceivers in CMOS," in Proceedings of IEEE International Symposium of Solid-State Circuits Conference 2008, ATAC Design Forum: Future of High-Speed Transceivers, Feb. 2008.
34. A. Nikoozadeh and B. Murmann, "An Analysis of Latch Comparator Offset Due to Load Capacitor Mismatch," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 12, pp. 1398-1402, Dec. 2006.
35. H. Veendrick, "The Behaviour of Flip-Flops Used as Synchronizers and Prediction of their Failure Rate," IEEE Journal of Solid-State Circuits, vol. 15, no. 2, pp. 169-176, Apr. 1980.
36. Y. Greshishchev, J. Aguirre, M. Besson, R. Gibbins, C. Falt, P. Flemke, N. Ben-Hamida, D. Pollex, P. Schvan, and S.-C. Wang, "A 40GS/s 6b ADC in 65nm CMOS," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2010, pp. 390-391.
37. G. Van der Plas, S. Decoutere, and S. Donnay, "A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2006, p. 2310.
38. W. Yu, S. Sen, and B. Leung, "Distortion Analysis of MOS Track-and-Hold Sampling Mixers using Time-Varying Volterra Series," IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 46, no. 2, pp. 101-113, Feb. 1999.
39. J. Steensgaard, "Bootstrapped Low-Voltage Analog Switches," in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 2, July 1999, pp. 29-32.
40. A. Abo and P. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May 1999.
41. J. B. Johnson, "Thermal Agitation of Electricity in Conductors," Phys. Rev., vol. 32, no. 1, p. 97, July 1928.
42. H. Nyquist, "Thermal Agitation of Electric Charge in Conductors," Phys. Rev., vol. 32, no. 1, pp. 110-113, July 1928.
43. T. Kobayashi, K. Nogami, T. Shirotori, and Y. Fujimoto, "A Current-Controlled Latch Sense Amplifier and a Static Power-Saving Input Buffer for Low-Power Architecture," IEEE Journal of Solid-State Circuits, vol. 28, no. 4, pp. 523-527, Apr. 1993.
44. C. Portmann and T. Meng, "Power-Efficient Metastability Error Reduction in CMOS Flash A/D Converters," IEEE Journal of Solid-State Circuits, vol. 31, no. 8, pp. 1132-1140, Aug. 1996.
45. P. Nuzzo, F. De Bernardinis, P. Terreni, and G. Van der Plas, "Noise Analysis of Regenerative Comparators for Reconfigurable ADC Architectures," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 55, no. 6, pp. 1441-1454, July 2008.
46. J. Kim, B. Leibowitz, J. Ren, and C. Madden, "Simulation and Analysis of Random Decision Errors in Clocked Comparators," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 8, pp. 1844-1857, Aug. 2009.
47. J. He, S. Zhan, D. Chen, and R. Geiger, "Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 911-919, May 2009.
48. J. Kim, K. D. Jones, and M. A. Horowitz, "Fast, Non-Monte-Carlo Estimation of Transient Performance Variation Due to Device Mismatch," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 57, no. 7, pp. 1746-1755, July 2010.
49. T. Matthews and P. Heedley, "A Simulation Method for Accurately Determining DC and Dynamic Offsets in Comparators," in Proceedings of Midwest Symposium on Circuits and Systems, vol. 2, Aug. 2005, pp. 1815-1818.
50. P. Figueiredo and J. Vital, "Kickback Noise Reduction Techniques for CMOS Latched Comparators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 7, pp. 541-545, July 2006.
51. T. Sundstrom and A. Alvandpour, "A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process," in Proceedings of International Conference on Mixed Design of Integrated Circuits and Systems, June 2007, pp. 195-198.
52. P. Nuzzo, G. Van der Plas, R. De Bernardinis, L. Van der Perre, B. Gyselinckx, and P. Terreni, "A 10.6mW/0.8pJ Power-Scalable 1GS/s 4b ADC in 0.18 μm CMOS with 5.8GHz ERBW," in Proceedings of ACM/IEEE Design Automation Conference, July 2006, pp. 873-878.
53. S. Park, Y. Palaskas, and M. Flynn, "A 4-GS/s 4-bit Flash ADC in 0.18 μm CMOS," IEEE Journal of Solid-State Circuits, vol. 42, no. 9, pp. 1865-1872, Sept. 2007.
54. K.-L. Wong and C.-K. Yang, "Offset Compensation in Comparators with Minimum Input- Referred Supply Noise," IEEE Journal of Solid-State Circuits, vol. 39, no. 5, pp. 837-840, May 2004.
55. J. Schoeff, "An Inherently Monotonic 12 Bit DAC," IEEE Journal of Solid-State Circuits, vol. 14, no. 6, pp. 904-911, Dec. 1979.
56. L. Samid, P. Volz, and Y. Manoli, "A Dynamic Analysis of a Latched CMOS Comparator," in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, June 2004, pp. I-181-4.
57. B. Verbruggen, P. Wambacq, M. Kuijk, and G. Van der Plas, "A 7.6 mW1.75 GS/s 5 Bit Flash A/D converter in 90 nm Digital CMOS," in VLSI Circuits Symposium, Digest of Technical Papers, June 2008, pp. 14-15.
58. F. Kaess, R. Kanan, B. Hochet, and M. Declercq, "New Encoding Scheme for High-Speed Flash ADCs," in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 1, June 1997, pp. 5-8.
59. E. Sail and M. Vesterbacka, "Thermometer-to-Binary Decoders for Flash Analog-to-Digital Converters," in Proceedings of European Conference on Circuit Theory and Design, Aug. 2007, pp. 240-243.
60. C. Paulus, H.-M. Bluthgen, M. Low, E. Sicheneder, N. Bruls, A. Courtois, M. Tiebout, and R. Thewes, "A 4GS/s 6b Flash ADC in 0.13 μm CMOS," in VLSI Circuits Symposium, Digest of Technical Papers, June 2004, pp. 420-423.
61. C. S. Wallace, "A Suggestion for a Fast Multiplier," IEEE Transactions on Electronic Computers, vol. EC-13, no. 1, pp. 14-17, Feb. 1964.
62. R. Kanan, F. Kaess, and M. Declercq, "A 640 mW High Accuracy 8-Bit 1 GHz Flash ADC Encoder," in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 2, June 1999, pp. 420-423.
63. M. Shinagawa, Y. Akazawa, and T. Wakimoto, "Jitter Analysis of High-Speed Sampling Systems," IEEE Journal of Solid-State Circuits, vol. 25, no. 1, pp. 220-224, Feb. 1990.
64. A. Abidi, "Phase Noise and Jitter in CMOS Ring Oscillators," IEEE Journal of Solid-State Circuits, vol. 41, no. 8, pp. 1803-1816, Aug. 2006.
65. T. Weigandt, B. Kim, and P. Gray, "Analysis of Timing Jitter in CMOS Ring Oscillators," in Proceedings of IEEE International Symposium on Circuits and Systems, vol. 4, May 1994, pp. 27-30.
66. A. Strak and H. Tenhunen, "Analysis of Timing Jitter in Inverters Induced by Power-Supply Noise," in Proceedings of International Conference on Design and Test of Integrated Systems in Nanoscale Technology, Sept. 2006, pp. 53-56.
67. X. Gao, B. Nauta, and E. Klumperink, "Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 55, no. 3, pp. 244-248, March 2008.
68. A. Boni, A. Pierazzi, and D. Vecchi, "LVDS I/O Interface for Gb/s-per-pin Operation in 0.35 μm CMOS ," IEEE Journal of Solid-State Circuits, vol. 36, no. 4, pp. 706-711, Apr. 2001.
69. M. Chen, J. Silva-Martinez, M. Nix, and M. Robinson, "Low-Voltage Low-Power LVDS Drivers," IEEE Journal of Solid-State Circuits, vol. 40, no. 2, pp. 472-479, Feb. 2005.
70. Texas Instruments, "TSW 1200 High Speed ADC LVDS Evaluation System," TSW1200 datasheet, Apr. 2007 [Revised Aug. 2008].
71. Nano River Technologies, "Miniboard: USB-I2C/SPI/GPIO Interface Adapter," MiniBoard user guide, Apr. 2009.
72. M. Bossche, J. Schoukens, and J. Renneboog, "Dynamic Testing and Diagnostics of A/D Converters," IEEE Transactions on Circuits and Systems, vol. 33, no. 8, pp. 775-785, Aug. 1986.
73. J. Simoes, J. Landeck, and C. Correia, "Nonlinearity of a Data-Acquisition System with Interleaving/Multiplexing," IEEE Transactions on Instrumentation and Measurement, vol. 46, no. 6, pp. 1274-1279, Dec. 1997.
74. R. Walden, "Performance Trends for Analog to Digital Converters," IEEE Communications Magazine, vol. 37, no. 2, pp. 96-101, Feb. 1999.
75. W. Cheng, W. Ali, M.-J. Choi, K. Liu, T. Tat, D. Devendorf, L. Linder, and R. Stevens, "A 3b 40GS/s ADC-DAC in 0.12 μm SiGe," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2004, pp. 262-263.
76. P. Schvan, D. Pollex, S.-C.Wang, C. Falt, and N. Ben-Hamida, "A 22GS/s 5b ADC in 0.13μm SiGe BiCMOS," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2006, pp. 2340-2349.
77. P. Schvan, J. Bach, C. Fait, P. Flemke, R. Gibbins, Y. Greshishchev, N. Ben-Hamida, D. Pollex, J. Sitch, S.-C. Wang, and J. Wolczanski, "A 24GS/s 6b ADC in 90nm CMOS," in Proceedings of IEEE International Solid-State Circuits Conference, vol. 1, Feb. 2008, pp. 544-634.
78. A. Nazemi, C. Grace, L. Lewyn, B. Kobeissy, O. Agazzi, P. Voois, C. Abidin, G. Eaton, M. Kargar, C. Marquez, S. Ramprasad, F. Bollo, V. Posse, S. Wang, and G. Asmanis, "A 10.3GS/s 6bit (5.1 ENOB at Nyquist) Time-Interleaved Pipelined ADC using Open-Loop Amplifiers and Digital Calibration in 90nm CMOS," in VLSI Circuits Symposium, Digest of Technical Papers, June 2008, pp. 18-19.
79. C.-C. Huang, C.-Y.Wang, and J.-T.Wu, "A CMOS 6-Bit 16-GS/s Time-Interleaved ADC with Digital Background Calibration," in VLSI Circuits Symposium, Digest of Technical Papers, June 2010, pp. 159-160.
80. B. Murmann, "ADC Performance Survey 1997-2010," [Online]. Available: http://www.stanford.edu/~murmann/adcsurvey.html.