A simulation method for accurately determining DC and dynamic offsets in comparators

Midwest Symposium on Circuits and Systems

Volumn 2005, Issue , 2005, Pages 1815-1818

  Matthews, Thomas W ^a   Heedley, Perry L ^a  

^a CALIFORNIA STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITIVE COUPLING; CHARGE INJECTION; HIGH-SPEED REGENERATIVE COMPARATORS; OFFSET VOLTAGE;

ANALOG TO DIGITAL CONVERSION; COMPARATORS (OPTICAL); ELECTRIC POTENTIAL; FLASH MEMORY;

COMPUTER SIMULATION;

EID: 33847111762     PISSN: 15483746     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MWSCAS.2005.1594475     Document Type: Conference Paper

References (3)

1. G. M. Yin, F. O. Eynde, W. Sansen, "A High-Speed CMOS Comparator with 8-b Resolution," IEEE J. Solid-State Circuits, vol. 27, pp. 208-211, February 1992.
2. Vilaysack Savengsveksa, Perry L Heedley, Thomas Matthews, Kamel Ahmad, Jose Negrete, "An 8-b 20-Msample/s Pipelined A/D Converter in 0.5-μm CMOS with 7.8 ENOB," to be published in Midwest Symposium on Circuits and Systems, Aug. 2005.
3. M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P.G. Welbers, "Matching Properties of MOS Transistors," IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct. 1989.