A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 43, Issue 4, 2008, Pages 778-785

  Louwsma, Simon M ^b   Van Tuijl, A J M ^a,b   Vertregt, Maarten ^a,c   Nauta, Bram ^a,b  

^a IEEE

^b UNIVERSITY OF TWENTE   (Netherlands)

^c NXP SEMICONDUCTORS   (Netherlands)

Author keywords

Analog to digital converter (ADC); Bandwidth mismatch; High speed sampling; Jitter; Pipeline; SAR; Successive approximation ADC (SA ADC); Time inter leaving; Time interleaved; Timing; Timing alignment; Track and hold (T H)

Indexed keywords

APPROXIMATION THEORY; BANDWIDTH; CMOS INTEGRATED CIRCUITS; ELECTRIC POWER UTILIZATION; ENERGY EFFICIENCY; JITTER; LOGIC CIRCUITS;

BANDWIDTH MISMATCH; HIGH SPEED SAMPLING; POWER EFFICIENCY; TIME INTER LEAVING; TIMING ALIGNMENT;

ANALOG TO DIGITAL CONVERSION;

EID: 41549143171     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2008.917427     Document Type: Conference Paper

References (11)

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