Advantages of Shift Registers Over DLLs for Flexible Low Jitter Multiphase Clock Generation

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 55, Issue 3, 2008, Pages 244-248

  Gao, Xiang ^a   Klumperink, Eric A M ^a   Nauta, Bram ^a  

^a UNIVERSITY OF TWENTE   (Netherlands)

Author keywords

Clock generation; current mode logic (CML); delay locked loop (DLL); divider; jitter; multiphase clocks; phase noise; shift register (SR); timing jitter

Indexed keywords

DIGITAL CIRCUITS; LOGIC CIRCUITS; PHASE NOISE; TIMING JITTER;

CLOCK GENERATION; CURRENT-MODE LOGIC; DELAY-LOCKED LOOP; MULTIPHASE CLOCK;

SHIFT REGISTERS;

EID: 42149125995     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2008.918972     Document Type: Article

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