LVDS I/O interface for Gb/s-per-pin operation in 0.35-μm CMOS

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 4, 2001, Pages 706-711

  Boni, Andrea ^a,b   Pierazzi, Andrea ^b   Vecchi, Davide ^b  

^a IEEE   (Italy)

^b UNIVERSITY OF PARMA   (Italy)

Author keywords

Back plane drivers; CMOS integrated circuits; High speed integrated circuits; Input output (I O); Low power design; Low voltage differential signaling (LVDS)

Indexed keywords

BACK PLANE DRIVERS; LOW POWER DESIGN; LOW VOLTAGE DIFFERENTIAL SIGNALING;

CLOSED LOOP CONTROL SYSTEMS; ELECTRIC POTENTIAL; ELECTRIC POWER SUPPLIES TO APPARATUS; INPUT OUTPUT PROGRAMS; INTERFACES (COMPUTER); THERMAL EFFECTS;

CMOS INTEGRATED CIRCUITS;

EID: 0035309966     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.913751     Document Type: Article

References (16)

1. The national technology roadmap for semiconductors
2. ECL-CMOS and CMOS-ECL interface in 1.2-μm CMOS for 150-MHz digital ECL data transmission systems
3. LVDS I/O buffers with a controlled reference circuit
4. Transmission line model generator (LMG)
5. A 5-Gb/s 8 × 8 ATM switch element CMOS LSI supporting five quality-of-service classes with 200-MHz LVDS interface
6. A 500-Mb/s 20-channel CMOS laser diode array driver for a parallel optical bus
7. 0.35-μm CMOS process parameters