A 3b 40GS/s ADC-DAC in 0.12μm SiGe

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 47, Issue , 2004, Pages

  Cheng, William ^a   Ali, Wals ^a   Choi, Moon Jung ^a   Liu, Kanon ^a   Tat, Tammy ^a   Devendorf, Don ^a   Linder, Lloyd ^a   Stevens, Ronald ^a  

^a TelASIC Communications Inc   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

FRONT END SIGNAL BANDWIDTH; RESISTOR NETWORKS; SINGLE-ENDED COUPLERS; STAGE RING OSCILLATORS;

BANDWIDTH; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; DEMULTIPLEXING; DIODES; PRINTED CIRCUIT DESIGN; RESISTORS; SEMICONDUCTING GERMANIUM; WAVEGUIDE COUPLERS;

ANALOG TO DIGITAL CONVERSION;

EID: 2442681512     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (4)

1. Tom Broekaert et al., "InP-HBT Optoelectronic Integrated Circuits for Photonic Analog-to-Digital Conversion," IEEE J Solid-State Circuits, vol. 36, no. 9, pp. 1335-1342, Sept. 2001.
2. Ken Poulton et al., "20GS/s 8 Bit ADC with a 1MB Memory in 0.1μm CMOS," ISSCC Dig. Tech. Papers, pp 318-319, Feb. 2003.
3. Jae-Sung Rieh et al., "Performance And Design Considerations For High Speed SiGe HBTs of Ft/Fmax = 375GHz/210GHz," Int. Conf. on Indium Phosphide and Related Materials, pp. 374-377, May 12-16, 2003.
4. Howard Johnson et al., "High Speed Digital Design," Prentice Hall, p. 7, 1993.