A dynamic analysis of a latched CMOS comparator

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2004, Pages

  Samid, Lourans ^a   Volz, Patrick ^a   Manoli, Yiannos ^a  

^a UNIVERSITY OF FREIBURG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; COMPUTATIONAL METHODS; COMPUTER SIMULATION; DIGITAL SIGNAL PROCESSING; ELECTRIC CLOCKS; ELECTRIC INVERTERS; ENERGY DISSIPATION; WAVE PROPAGATION; WIRELESS TELECOMMUNICATION SYSTEMS;

COMPERATORS; PARAMETER OPTIMIZATION; POWER CONSUMPTION; TRADEOFFS;

CMOS INTEGRATED CIRCUITS;

EID: 4344569720     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2004.1328161     Document Type: Conference Paper

References (3)

1. T. Byunghak Cho et. al., "A 10 b, 20 Msample/s, 35 mW Pipeline A/D Converter," IEEE Journal of Solid-State circuits, Vol. 30, No. 3, March 1995.
2. H. Klar, Integrierte Digitale Schaltungen MOS/BICMOS, Springer-Verlag, 1996.
3. M. Steyaert et. al., "High-Speed Accurate CMOS Comparator," Electronics Letters, Vol. 24, No. 16, 1988.