A 4.8-6.4-Gb/s serial link for backplane applications using decision feedback equalization

IEEE Journal of Solid-State Circuits

Volumn 40, Issue 9, 2005, Pages 1957-1965

  Balan, Vishnu ^a   Caroselli, Joe ^a   Chern, Jenn Gang ^b   Chow, Catherine ^a   Dadi, Ratnakar ^b   Desai, Chintan ^a   Fang, Leo ^a   Hsu, David ^a   Joshi, Pankaj ^a   Kimura, Hiroshi ^b   Liu, Cathy Ye ^a   Pan, Tzu Wang ^a   Park, Ryan ^a   You, Cindy ^b   Zeng, Yi ^a   Zhang, Eric ^a   Zhong, Freeman ^a  

^a AGERE SYSTEMS   (United States)

^b Link A Media Devices Corporation   (United States)

Author keywords

Adaptive equalization; Backplane transceiver; Decision feedback equalization (DFE); SerDes; Serial link

Indexed keywords

CMOS INTEGRATED CIRCUITS; DECISION THEORY; TRANSCEIVERS;

ADAPTIVE EQUALIZATION; BACKPLANE TRANSCEIVER; DECISION FEEDBACK EQUALIZATION (DFE); SERDES; SERIAL LINK;

TRANSMITTERS;

EID: 25144506481     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.848180     Document Type: Conference Paper

References (8)

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