An 8× 5 Gb/s parallel receiver with collaborative timing recovery

IEEE Journal of Solid-State Circuits

Volumn 44, Issue 11, 2009, Pages 3120-3130

  Agrawal, Ankur ^a   Liu, Andrew ^b   Hanumolu, Pavan Kumar ^c   Wei, Gu Yeon ^a  

^a HARVARD UNIVERSITY   (United States)

^b MATHWORKS INC   (United States)

^c 1148 Kelley Engineering Center Corvallis   (United States)

Author keywords

Clock and data recovery; High speed serial link; Jitter tolerance; Jitter tracking bandwidth; Parallel receiver; Source synchronous link

Indexed keywords

CLOCK AND DATA RECOVERY; HIGH-SPEED SERIAL LINK; JITTER TOLERANCE; PARALLEL RECEIVER; SOURCE-SYNCHRONOUS LINK;

BANDWIDTH; COMPUTER SYSTEM RECOVERY; DISTRIBUTED COMPUTER SYSTEMS; PHASE INTERFACES; RECOVERY; TIME MEASUREMENT; TIMING JITTER;

CLOCKS;

EID: 70449475603     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2009.2033399     Document Type: Article

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