A 12.5Gb/s serdes in 65 nm CMOS using a baud-rate ADC with digital receiver equalization and clock recovery

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages 436-438

  Harwood, Mike ^a   Warke, Nirmal ^a   Simpson, Richard ^a   Leslie, Tom ^a   Amerasekera, Ajith ^a   Batty, Sean ^a   Colman, Derek ^a   Carr, Eugenia ^a   Gopinathan, Venu ^b   Hubbins, Steve ^a   Hunt, Peter ^a   Joy, Andy ^a   Khandelwal, Pulkit ^a   Killips, Bob ^a   Krause, Thomas ^a   Lytollis, Shaun ^a   Pickering, Andy ^a   Saxton, Mark ^a   Sebastio, David ^a   Swanson, Graeme ^a   Szczepanek, Andre ^a   Ward, Terry ^a   Williams, Jeff ^a   Williams, Richard ^a   Willwerth, Tom ^a   more..

^a TEXAS INSTRUMENTS   (United States)

^b TEXAS INSTRUMENTS   (India)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; BIT ERROR RATE; ELECTRIC LOSSES; ELECTRIC POWER UTILIZATION; SIGNAL RECEIVERS;

BACKPLANE DATA COMMUNICATION; CHANNEL COMPENSATION; CLOCK RECOVERY; DIGITAL RECEIVER EQUALIZATION; DIGITAL RECEIVERS;

CMOS INTEGRATED CIRCUITS;

EID: 34548835238     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373481     Document Type: Conference Paper

References (7)

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