A 22-Gb/s PAM-4 receiver in 90-nm CMOS SOI technology

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 4, 2006, Pages 954-964

  Toifl, Thomas ^a,b   Menolfi, Christian ^a,b   Ruegg, Michael ^a,c,d   Reutemann, Robert ^a,c   Buchmann, Peter ^b,e,f   Kossel, Marcel ^a,b   Morf, Thomas ^a,b   Weiss, Jonas ^a,b   Schmatz, Martin L ^a,b,g  

^a IEEE   (Switzerland)

^b IBM RESEARCH ZURICH   (Switzerland)

^c Miromico AG   (Switzerland)

^d INFINEON TECHNOLOGIES   (United States)

^e MESFET Technology

^f Swiss Physical Society   (Switzerland)

^g IBM RESEARCH   (United States)

Author keywords

CML; CMOS; Digital communication; Latch; PAM 4; Receiver; Serial links; SOI

Indexed keywords

LATCH; PAM-4; SERIAL LINKS; SOI;

AMPLIFIERS (ELECTRONIC); CMOS INTEGRATED CIRCUITS; DIGITAL COMMUNICATION SYSTEMS; ELECTRIC POWER UTILIZATION; EMITTER COUPLED LOGIC CIRCUITS; PULSE MODULATION; SIGNAL PROCESSING;

SIGNAL RECEIVERS;

EID: 33645689849     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2006.870898     Document Type: Conference Paper

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